coreboot-gerrit September 2024

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/6edc5d15_9252b90b?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > Subrata, > pmc_enable_gpe() and pmc_enable_std_gpe() are removed. GPE EN bits are enabled in kernel during boot. even if we set those bits in CB, they are over-written by kernel. I don't see a caller for `pmc_enable_gpe` and `pmc_enable_std_gpe` but there is no harm in extending the functionality of this API to allow to enable GPE1. I can't think of a usevcase beyond if any HW person wish to test the GPE capability alone w/o bothering booting to OS (like we have FW shell to play with the chipset). -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 04:38:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Jérémy Compostella (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Pratikkumar V Prajapati, Saurabh Mishra, Subrata Banik. Jérémy Compostella has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... Patch Set 16: (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/dfd945b1_70596801?us… : PS16, Line 24: #ifndef BIT_FLAG_32 Any chance we could have a short comment to explain why we do not define the more common BIT_32(x) macro. What about? ``` /* * This macro declares a bit as a 32-bits unsigned integer. The common BIT_32(x) macro is already defined by some external header file. To avoid any conflicts, we used a different name. */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 16 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 04:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/cbfstool: Print max empty entry size in error message
by Yidi Lin (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Julius Werner, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84204?usp=email ) Change subject: util/cbfstool: Print max empty entry size in error message ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84204/comment/1f9abed4_b0707b55?us… : PS1, Line 9: print prints -- To view, visit https://review.coreboot.org/c/coreboot/+/84204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Gerrit-Change-Number: 84204 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 04:36:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbfstool: Print max empty entry size in error message
by Yu-Ping Wu (Code Review) 04 Sep '24

04 Sep '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84204?usp=email ) Change subject: util/cbfstool: Print max empty entry size in error message ...................................................................... util/cbfstool: Print max empty entry size in error message Currently, cbfstool print the following error message when the added file doesn't fit in the region: E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big? It requires manual inspection to know the space left in the region. To make that easier, also print the maximum empty CBFS entry size in the error message: E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0; Largest empty slot: 512 bytes Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M util/cbfstool/cbfs_image.c 1 file changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84204/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 740a3b2..e935357 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -743,6 +743,8 @@ uint32_t entry_type; uint32_t addr, addr_next; + uint32_t entry_size; + uint32_t max_null_entry_size = 0; struct cbfs_file *entry, *next; uint32_t need_size; uint32_t header_size = be32toh(header->offset); @@ -766,9 +768,11 @@ addr = cbfs_get_entry_addr(image, entry); next = cbfs_find_next_entry(image, entry); addr_next = cbfs_get_entry_addr(image, next); + entry_size = addr_next - addr; + max_null_entry_size = MAX(max_null_entry_size, entry_size); DEBUG("cbfs_add_entry: space at 0x%x+0x%x(%d) bytes\n", - addr, addr_next - addr, addr_next - addr); + addr, entry_size, entry_size); /* Will the file fit? Don't yet worry if we have space for a new * "empty" entry. We take care of that later. @@ -803,7 +807,7 @@ } DEBUG("section 0x%x+0x%x for content_offset 0x%x.\n", - addr, addr_next - addr, content_offset); + addr, entry_size, content_offset); if (cbfs_add_entry_at(image, entry, buffer->data, content_offset, header, len_align) == 0) { @@ -812,8 +816,10 @@ break; } - ERROR("Could not add [%s, %zd bytes (%zd KB)@0x%x]; too big?\n", - buffer->name, buffer->size, buffer->size / 1024, content_offset); + ERROR("Could not add %s [header %d + content %zd bytes (%zd KB)] @0x%x; " + "Largest empty slot: %d bytes\n", + buffer->name, header_size, buffer->size, buffer->size / 1024, content_offset, + max_null_entry_size); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Gerrit-Change-Number: 84204 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Saurabh Mishra (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Subrata Banik. Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84142?usp=email to look at the new patch set (#16). Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... src/include: Introduce a new BIT_FLAG_32(x) macro Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the designated bit set. This ensures compatibility with the 32-bit 'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and could potentially cause an overflow when shifted beyond 31 bits. Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/types.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 16 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[XS] Change in coreboot[main]: Cezanne: Add an option to enable A/B recovery scheme
by Bao Zheng (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84195?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Cezanne: Add an option to enable A/B recovery scheme ...................................................................... Cezanne: Add an option to enable A/B recovery scheme The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B. The Cezanne platform supports both A/B recovery and no recovery method and need this flag passed to amdfwtool to enable/disable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: amdfwtool: Set L2 table size as 0x400
by Bao Zheng (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Felix Held, Zheng Bao, ritul guru. Hello Anand Vaikar, Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84194?usp=email to look at the new patch set (#2). Change subject: amdfwtool: Set L2 table size as 0x400 ...................................................................... amdfwtool: Set L2 table size as 0x400 The Max size of L2 table is 0x400. If we set it to other value, the the A/B recovery image can not boot on Cezanne/Majolica platform. The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards are binary identical. Tested on Skyrim and image can boot. Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/84194/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Gerrit-Change-Number: 84194 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jian Tong, Karthik Ramasubramanian, Kun Liu, Shelley Chen. Subrata Banik has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84198?usp=email ) Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 3 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 03:45:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel: Remove unused `GPIO_IRQ_xxx` definitions
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84182?usp=email ) Change subject: soc/intel: Remove unused `GPIO_IRQ_xxx` definitions ...................................................................... soc/intel: Remove unused `GPIO_IRQ_xxx` definitions This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake, Meteor Lake and Tiger Lake. These definitions are no longer needed. TEST=Able to build and boot google/xol and google/karis. Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/itss.h M src/soc/intel/cannonlake/include/soc/itss.h M src/soc/intel/elkhartlake/include/soc/itss.h M src/soc/intel/jasperlake/include/soc/itss.h M src/soc/intel/meteorlake/include/soc/itss.h M src/soc/intel/tigerlake/include/soc/itss.h 6 files changed, 0 insertions(+), 18 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/include/soc/itss.h b/src/soc/intel/alderlake/include/soc/itss.h index ff26c9f..0ea8ff1 100644 --- a/src/soc/intel/alderlake/include/soc/itss.h +++ b/src/soc/intel/alderlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_ADL_ITSS_H #define SOC_INTEL_ADL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h index 59a2887f..902b8e2 100644 --- a/src/soc/intel/cannonlake/include/soc/itss.h +++ b/src/soc/intel/cannonlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_CNL_ITSS_H #define SOC_INTEL_CNL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) diff --git a/src/soc/intel/elkhartlake/include/soc/itss.h b/src/soc/intel/elkhartlake/include/soc/itss.h index a550f4c..90a4af2 100644 --- a/src/soc/intel/elkhartlake/include/soc/itss.h +++ b/src/soc/intel/elkhartlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_EHL_ITSS_H #define SOC_INTEL_EHL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h index c088865..ba1a1c2 100644 --- a/src/soc/intel/jasperlake/include/soc/itss.h +++ b/src/soc/intel/jasperlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_JSL_ITSS_H #define SOC_INTEL_JSL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) diff --git a/src/soc/intel/meteorlake/include/soc/itss.h b/src/soc/intel/meteorlake/include/soc/itss.h index a0347d6..cee8245 100644 --- a/src/soc/intel/meteorlake/include/soc/itss.h +++ b/src/soc/intel/meteorlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_MTL_ITSS_H #define SOC_INTEL_MTL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) diff --git a/src/soc/intel/tigerlake/include/soc/itss.h b/src/soc/intel/tigerlake/include/soc/itss.h index 20abbee..0291dc8 100644 --- a/src/soc/intel/tigerlake/include/soc/itss.h +++ b/src/soc/intel/tigerlake/include/soc/itss.h @@ -3,9 +3,6 @@ #ifndef SOC_INTEL_TGL_ITSS_H #define SOC_INTEL_TGL_ITSS_H -#define GPIO_IRQ_START 50 -#define GPIO_IRQ_END ITSS_MAX_IRQ - #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) -- To view, visit https://review.coreboot.org/c/coreboot/+/84182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76 Gerrit-Change-Number: 84182 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Remove unused pch_handle_sideband() function
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84189?usp=email ) Change subject: soc/intel/meteorlake: Remove unused pch_handle_sideband() function ...................................................................... soc/intel/meteorlake: Remove unused pch_handle_sideband() function This change removes the unused pch_handle_sideband() function from the Meteor Lake platform code. TEST=Able to build and boot google/rex. Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/meteorlake/finalize.c 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: Eric Lai: Looks good to me, approved Pratikkumar V Prajapati: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index ed29ba9..1fd1d98 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -23,21 +23,13 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> -static void pch_handle_sideband(config_t *config) -{ -} - static void pch_finalize(void) { - config_t *config = config_of_soc(); - /* TCO Lock down */ tco_lockdown(); /* TODO: Add Thermal Configuration */ - pch_handle_sideband(config); - pmc_clear_pmcon_sts(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Gerrit-Change-Number: 84189 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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