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I'd like you to reexamine a change. Please visit
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Change subject: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO
......................................................................
[NOT_FOR_MERGE]Kconfig: Build all targets with LTO
ARM with GCC LTO fails hard.
Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84033/30
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Change subject: include/spd_bin.h: Add 3 SPD IO functions
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84201/comment/0d388acd_67369a63?us… :
PS2, Line 10: default implementation is to forward to SMBus IO functions directly.
revise as? By default, PCH SMBus codes will be called to retrieve SPD data. Add a separate IO layer so that SoC could provide another implementation of SPD IO functions such as ...
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Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro
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Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84142/comment/e2e04ece_0841123b?us… :
PS17, Line 11: 1ul is 64 bits wide
Is it true even for 32 bit systems?
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Change subject: soc/intel/common/systemagent: Fixup systemagent address
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Patch Set 16: Code-Review+1
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Change subject: soc/intel/common/systemagent: Fixup systemagent address
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Patch Set 16:
(1 comment)
File src/soc/intel/common/block/systemagent/systemagent_def.h:
https://review.coreboot.org/c/coreboot/+/83318/comment/3e22038e_d0a15681?us… :
PS13, Line 78: const char *description;
> Maybe add a bool need_soc_fixup field and set the field in sa_mem_map_descriptor init (e.g. […]
Done
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Change subject: soc/intel/common/systemagent: Fixup systemagent address
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Patch Set 16:
(1 comment)
File src/soc/intel/common/block/systemagent/Kconfig:
https://review.coreboot.org/c/coreboot/+/83318/comment/23fb0881_55944b72?us… :
PS15, Line 65: config HAVE_TSEG_LIMIT_REGISTER
> Done, please see https://review.coreboot. […]
Done
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Change subject: soc/intel/common/systemagent: Fixup systemagent address
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Patch Set 16:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83318/comment/c6bd77e9_17108d23?us… :
PS15, Line 14: soc_systemagent_fixup_address() to improve it.
> Commit message doesn't describe the TSEG limit changes.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83318/comment/cfd8ea02_1d36bb04?us… :
PS15, Line 14: soc_systemagent_fixup_address() to improve it.
to improve it -> to handle the special cases.
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Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
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Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84200/comment/62aba1a5_180d2613?us… :
PS1, Line 9: Systemagent assumes GSM region is next to TSEG region, but some SoC may
System agent
https://review.coreboot.org/c/coreboot/+/84200/comment/2a8eb766_76227b25?us… :
PS1, Line 11: On such platforms, TSEG region is limited by the TSEG limit register,
defined
https://review.coreboot.org/c/coreboot/+/84200/comment/6b353f93_ecd61e4e?us… :
PS1, Line 12: and the default offset for that is (TSEG + 4).
I guess you are meaning the register offset of TSEG limit is TSEG base + 4, right?
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Change subject: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
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Patch Set 2:
(1 comment)
Patchset:
PS2:
Is the signing token for Guybrush already present? If not, please add that too in this CL.
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Change subject: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries
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Patch Set 2: Code-Review+2
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