coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#81). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h M src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 42 files changed, 3,743 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/81 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 81 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Saurabh Mishra (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... Patch Set 14: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84142/comment/29d0bc1a_0058df3e?us… : PS14, Line 7: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. > Remove the . at the end of line. Acknowledged https://review.coreboot.org/c/coreboot/+/84142/comment/d61efe96_961fc49d?us… : PS14, Line 9: This new macro addition ensures the shift operation does not > This is a generic macro. Please describe the macro here. […] Acknowledged https://review.coreboot.org/c/coreboot/+/84142/comment/21046f58_a8f90382?us… : PS14, Line 12: On a 64-bit system, 1ul will typically be 64 bits wide. : The left shift can accommodate values of x up to 63 without overflowing. : But `GEN_PMCON_A` register width is 32-bit hence, adding new SET_32_BIT_FLAG(x) : to limit the register to max 32-bit width. > yes Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 03:34:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Saurabh Mishra (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Subrata Banik. Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84142?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Code-Review-1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... src/include: Introduce a new BIT_FLAG_32(x) macro This commit introduces the BIT_FLAG_32 macro, which generates a 32-bit mask with a specified bit set. On a 64-bit system, 1ul will typically be 64 bits wide. The left shift can accommodate values of x up to 63 without overflowing. But `GEN_PMCON_A` register width is 32-bit hence, adding new BIT_FLAG_32(x) to limit the register to max 32-bit width. Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/types.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 15 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
by Saurabh Mishra (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84142/comment/7996cca8_ce6cc8d6?us… : PS14, Line 7: src/include: Introducing a new SET_32_BIT_FLAG(x) macro. > Introduce Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 14 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 03:30:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Yu-Ping Wu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 03:09:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Configure cpu power limits by battery status
by Jian Tong (Code Review) 04 Sep '24

04 Sep '24

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84202?usp=email ) Change subject: mb/google/brox/var/lotso: Configure cpu power limits by battery status ...................................................................... mb/google/brox/var/lotso: Configure cpu power limits by battery status When battery not persent, limit PL4 to 40. BUG=b:355094551 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/Makefile.mk M src/mainboard/google/brox/variants/lotso/overridetree.cb A src/mainboard/google/brox/variants/lotso/ramstage.c 3 files changed, 79 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/84202/1 diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk index c88fed9..6c3ef5a 100644 --- a/src/mainboard/google/brox/variants/lotso/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -5,3 +5,4 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += ramstage.c \ No newline at end of file diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 85a3506..78d73b3 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -74,8 +74,7 @@ register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 40, - .tdp_pl4 = 57, + .tdp_pl2_override = 25, }" device domain 0 on diff --git a/src/mainboard/google/brox/variants/lotso/ramstage.c b/src/mainboard/google/brox/variants/lotso/ramstage.c new file mode 100644 index 0000000..075ccb9 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/ramstage.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ + +const struct cpu_power_limits performance_efficient_limits[] = { + { + .mchid = PCI_DID_INTEL_RPL_P_ID_3, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 25000, + .pl2_max_power = 25000, + .pl4_power = 114000 + }, + { + .mchid = PCI_DID_INTEL_RPL_P_ID_4, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 25000, + .pl2_max_power = 25000, + .pl4_power = 114000 + }, +}; + +const struct cpu_power_limits power_optimized_limits[] = { + { + .mchid = PCI_DID_INTEL_RPL_P_ID_3, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 25000, + .pl2_max_power = 25000, + .pl4_power = 40000 + }, + { + .mchid = PCI_DID_INTEL_RPL_P_ID_4, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 25000, + .pl2_max_power = 25000, + .pl4_power = 40000 + }, +}; + +void __weak variant_devtree_update(void) +{ + + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + const struct cpu_power_limits *limits = performance_efficient_limits; + size_t limits_size = ARRAY_SIZE(performance_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = power_optimized_limits; + limits_size = ARRAY_SIZE(power_optimized_limits); + } + } + + variant_update_power_limits(limits, limits_size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Gerrit-Change-Number: 84202 Gerrit-PatchSet: 1 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Jian Tong (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Kun Liu, Shelley Chen, Subrata Banik. Hello Karthik Ramasubramanian, Kun Liu, Shelley Chen, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84198?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Kun Liu, Verified+1 by build bot (Jenkins) Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... mb/google/brox/var/lotso: remove unused cam enable_gpio Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84198/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 3 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/systemagent: Fix grammer in comments
by Nicholas Chin (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com. Nicholas Chin has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84199?usp=email ) Change subject: soc/intel/common/systemagent: Fix grammer in comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Gerrit-Change-Number: 84199 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 02:24:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Kun Liu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jian Tong. Kun Liu has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84198?usp=email ) Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 01:37:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Jian Tong (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Kun Liu. Hello Kun Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84198?usp=email to look at the new patch set (#2). Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... mb/google/brox/var/lotso: remove unused cam enable_gpio Based on schematics nb7228a_lotso_intel_mb_fvt_20240724A.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84198/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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