coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84198?usp=email ) Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... mb/google/brox/var/lotso: remove unused cam enable_gpio Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 09e8815..85a3506 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -281,8 +281,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" device ref usb2_port6 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84177?usp=email ) Change subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support ...................................................................... mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1. lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177 Reviewed-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Kun Liu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 0f87889..09e8815 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -357,6 +357,7 @@ .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" -- To view, visit https://review.coreboot.org/c/coreboot/+/84177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607 Gerrit-Change-Number: 84177 Gerrit-PatchSet: 7 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brox/variants/brox: Update PL1 Min
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83661?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox/variants/brox: Update PL1 Min ...................................................................... mb/google/brox/variants/brox: Update PL1 Min Update PL1 Min value from 6W to 15W based on the brox thermal cooling capacity and hardware design. BUG=None BRANCH=None TEST=Build and boot on brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/brox/ramstage.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c index c81dd7e..78e03ca 100644 --- a/src/mainboard/google/brox/variants/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/brox/ramstage.c @@ -16,7 +16,7 @@ { .mchid = PCI_DID_INTEL_RPL_P_ID_3, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000, @@ -25,7 +25,7 @@ { .mchid = PCI_DID_INTEL_RPL_P_ID_4, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000, -- To view, visit https://review.coreboot.org/c/coreboot/+/83661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Gerrit-Change-Number: 83661 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/i2c/generic: Remove erroneous acpigen_pop_len
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84197?usp=email ) Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len ...................................................................... drivers/i2c/generic: Remove erroneous acpigen_pop_len There are one too many acpigen_pop_len calls in the code to generate the ROTM; remove one to fix an EMERG warning: [EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38 The extra acpigen_pop_len() call was added commit 45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package"). Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/i2c/generic/generic.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 27bef49..260ea83 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -165,7 +165,6 @@ acpigen_write_return_namestr("RBUF"); acpigen_pop_len(); - acpigen_pop_len(); } /* Chip Direct Mapping */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b Gerrit-Change-Number: 84197 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: intelp2m: add support for elkhartlake
by Maxim (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Alexander Couzens. Maxim has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) Change subject: intelp2m: add support for elkhartlake ...................................................................... Patch Set 3: (6 comments) Patchset: PS3: Thanks for this work! It seems that the code in all methods is the same as the Apollo Lake platform (https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util…), except for `func (Platform Specific) Pull() {...}`. And if so, we can reuse these methods. It is necessary to define InheritanceMacro : apl.Platform Specific{} inside the structure for the new platform and make calls in the appropriate methods. (for example, for Cannon Lake - https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util…) File util/intelp2m/platforms/ehl/macro.go: https://review.coreboot.org/c/coreboot/+/84191/comment/5caf1b86_411e922b?us… : PS3, Line 151: func (PlatformSpecific) GpiMacroAdd() { ```go // Adds PAD_CFG_GPI macro with arguments func (PlatformSpecific) GpiMacroAdd() { platform.InheritanceMacro.GpiMacroAdd() } ``` https://review.coreboot.org/c/coreboot/+/84191/comment/23fa57ec_7f4a90e5?us… : PS3, Line 204: func (PlatformSpecific) GpoMacroAdd() { ```go // Adds PAD_CFG_GPO macro with arguments func (platform PlatformSpecific) GpoMacroAdd() { platform.InheritanceMacro.GpoMacroAdd() } ``` https://review.coreboot.org/c/coreboot/+/84191/comment/11d578d5_622929a8?us… : PS3, Line 236: func (PlatformSpecific) NativeFunctionMacroAdd() { ```go // Adds PAD_CFG_NF macro with arguments func (platform PlatformSpecific) NativeFunctionMacroAdd() { platform.InheritanceMacro.NativeFunctionMacroAdd() } ``` https://review.coreboot.org/c/coreboot/+/84191/comment/ff3a718a_fd94b7cd?us… : PS3, Line 268: func (PlatformSpecific) NoConnMacroAdd() { ```go // Adds PAD_NC macro func (platform PlatformSpecific) NoConnMacroAdd() { platform.InheritanceMacro.NoConnMacroAdd() } ``` https://review.coreboot.org/c/coreboot/+/84191/comment/d839a88b_5cd5027e?us… : PS3, Line 302: macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet()) ```go macro := common.GetInstanceMacro( PlatformSpecific{ InheritanceMacro: apl.PlatformSpecific{}, }, fields.InterfaceGet(), ) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 06 Sep 2024 12:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Bao Zheng (Code Review) 06 Sep '24

06 Sep '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84233?usp=email ) Change subject: amdfwtool: Add combo new layout for new family ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
by Yu-Ping Wu (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/84221?usp=email ) Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/84221/comment/bbc33c56_b60c387d?us… : PS1, Line 37: val_regs Can we rename it to `gpio_val_regs`? -- To view, visit https://review.coreboot.org/c/coreboot/+/84221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Gerrit-Change-Number: 84221 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 10:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Update touchscreen power sequence
by Weimin Wu (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Tongtong Pan. Weimin Wu has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/84196?usp=email ) Change subject: mb/google/dedede/var/awasuki: Update touchscreen power sequence ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: > any spec change? No spec for stop_delay_ms, when resume the sequence is VTSP => RST => TP_EN(stop), TP_EN(stop) is last phase. -------------------------------------------------------------------- Before changed: elants_i2c i2c-ELAN0001:00: PM: acpi_subsys_resume+0x0/0x60 returned 0 after 449906 usecs the seconds_system_resume > 0.5 seconds, power_UiResume test failed. -------------------------------------------------------------------- After changed: elants_i2c i2c-ELAN0001:00: PM: acpi_subsys_resume+0x0/0x60 returned 0 after 161712 usecs the seconds_system_resume < 0.5 seconds, passed power_UiResume test. and Passed power_SuspendStress.bareFSI 2500 cycles test, touchscreen still working functionally. Commit Message: https://review.coreboot.org/c/coreboot/+/84196/comment/d1c27fd3_adf5897e?us… : PS3, Line 9: Reduce resume time. > Have you confirmed that the touchscreen works even after multiple iterations of suspend/resume. […] Passed power_SuspendStress.bareFSI 2500 cycles test, touchscreen still working functionally. -- To view, visit https://review.coreboot.org/c/coreboot/+/84196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Gerrit-Change-Number: 84196 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 09:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: nb/intel/sandybridge: Add Kconfig to set default IGD allocation
by Angel Pons (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Matt DeVillier. Angel Pons has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84225?usp=email ) Change subject: nb/intel/sandybridge: Add Kconfig to set default IGD allocation ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/northbridge/intel/sandybridge/Kconfig: https://review.coreboot.org/c/coreboot/+/84225/comment/a2b499ac_614b15c6?us… : PS3, Line 204: IGD_DEFAULT_INT_VALUE > is IGD_DEFAULT_UMA_INDEX better? Good enough, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/84225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Gerrit-Change-Number: 84225 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 08:38:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 89: (1 comment) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/5a137350_2164acaf?us… : PS37, Line 30: C_STATE_C0, /* 0 */ : C_STATE_C1, /* 1 */ : C_STATE_C1E, /* 2 */ : C_STATE_C6_SHORT_LAT, /* 3 */ : C_STATE_C6_LONG_LAT, /* 4 */ : C_STATE_C7_SHORT_LAT, /* 5 */ : C_STATE_C7_LONG_LAT, /* 6 */ : C_STATE_C7S_SHORT_LAT, /* 7 */ : C_STATE_C7S_LONG_LAT, /* 8 */ : C_STATE_C8, /* 9 */ : C_STATE_C9, /* 10 */ : C_STATE_C10, /* 11 */ : NUM_C_STATES > > I will come back with the data, checking Internally with c states owner. […] Hi, I will be back on this info. Checking internally with the owners. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 89 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 07:32:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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