coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
3342 discussions

[M] Change in coreboot[main]: soc/intel/apollolake: Add support for IFWI Measured Boot
by Werner Zeh (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Sean Rhodes. Werner Zeh has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/65272?usp=email ) Change subject: soc/intel/apollolake: Add support for IFWI Measured Boot ...................................................................... Patch Set 52: (4 comments) File src/soc/intel/apollolake/Makefile.mk: https://review.coreboot.org/c/coreboot/+/65272/comment/3f80a6a8_810b21f0?us… : PS50, Line 10: bootblock-y > Done I guess you mixed it up here, or? My comment was to change line 10, not line 8. The entriy in line 8 was OK so. File src/soc/intel/apollolake/measured_boot.c: https://review.coreboot.org/c/coreboot/+/65272/comment/b73bd18e_5d63d3ab?us… : PS35, Line 18: *(uint64_t *)(uint32_t)(BASE_4GB - 0x40); > I think you should use the readx ops here. […] This should be solved with the latest patch set. File src/soc/intel/apollolake/measured_boot.c: https://review.coreboot.org/c/coreboot/+/65272/comment/e44ec128_a455ec37?us… : PS50, Line 19: read32((uint64_t *)(BASE_4GB - 0x40)); > Not going to pretend I follow entirely, but seems to not break anything! It is basically the same offset you are hard coded before. If this works then I am fine. https://review.coreboot.org/c/coreboot/+/65272/comment/04ebd7a4_31134d07?us… : PS50, Line 67: sizeof(bpm_info->txe_hash) - 1) > Like that? Yes, this looks better IMO. -- To view, visit https://review.coreboot.org/c/coreboot/+/65272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61ce4a34875d6d3357d4088167cdd887bafdff23 Gerrit-Change-Number: 65272 Gerrit-PatchSet: 52 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 05:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Bao Zheng (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84233?usp=email to review the following change. Change subject: amdfwtool: Add combo new layout for new family ...................................................................... amdfwtool: Add combo new layout for new family The A/B recovery layout has a new way to support combo. It packs multiple entries into PSP L1 directory. TEST=Identical test on all AMD platform Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1d94e06..6aac03a 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1610,6 +1610,8 @@ open_process_config(cb_config.config, &cb_config); + if (cb_config.soc_id == PLATFORM_PHOENIX) + cb_config.combo_new_rab = true; ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { fprintf(stderr, "Error: Failed to allocate memory\n"); @@ -1664,7 +1666,7 @@ cb_config.signed_start_addr, cb_config.soc_id); - if (cb_config.use_combo) { + if (cb_config.use_combo && !cb_config.combo_new_rab) { ctx.psp_combo_dir = new_combo_dir(&ctx, PSP2_COOKIE); adjust_current_pointer(&ctx, 0, 0x1000U); @@ -1677,11 +1679,11 @@ if (cb_config.config) cb_config.combo_config[0] = cb_config.config; + ctx.pspdir = NULL; do { if (cb_config.use_combo && cb_config.debug) printf("Processing %dth combo entry\n", combo_index); - ctx.pspdir = NULL; ctx.pspdir2 = NULL; ctx.pspdir2_b = NULL; ctx.biosdir = NULL; @@ -1735,7 +1737,9 @@ */ ctx.pspdir2_b = NULL; /* More explicitly */ } - integrate_psp_firmwares(&ctx, + if ((combo_index == 0 && cb_config.combo_new_rab) || + !cb_config.combo_new_rab) + integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); integrate_psp_levels(&ctx, &cb_config); } else { @@ -1744,9 +1748,10 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); } - if (!cb_config.use_combo) { + if (!cb_config.use_combo || (cb_config.combo_new_rab && combo_index == 0)) { + /* For new combo layout, there is only 1 PSP level 1 directory. */ fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); - } else { + } else if (cb_config.use_combo && !cb_config.combo_new_rab) { fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config); /* 0 -Compare PSP ID, 1 -Compare chip family ID */ assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 7ca7d89..60a3754 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -426,6 +426,7 @@ bool recovery_ab_single_copy; bool need_ish; bool use_combo; + bool combo_new_rab; bool have_apcb_bk; enum platform soc_id; -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Derek Huang, Felix Held, Ivan Chen, Karthik Ramasubramanian, Paul Menzel. Kevin Yang has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Sep 2024 02:41:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Bao Zheng (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/bd155a6c_0be31c24?us… : PS1, Line 9: Non A/B recovery > Wow, thank you for the additional detail. But please also mention the NDA spec #56995. Done Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/1441c568_2315336d?us… : PS2, Line 7: Cezanne: Add an option to enable A/B recovery scheme : > One more nit, please begin this with "soc/amd/cezanne". […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Sep 2024 02:33:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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[XS] Change in coreboot[main]: amdfwtool: Set L2 table size as 0x400
by Bao Zheng (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Hello Anand Vaikar, Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84194?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Marshall Dawson, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: amdfwtool: Set L2 table size as 0x400 ...................................................................... amdfwtool: Set L2 table size as 0x400 The Max size of L2 table is 0x400. If we set it to other value, the the A/B recovery image can not boot on Cezanne/Majolica platform. The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards are binary identical. Tested on Skyrim and image can boot. Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/84194/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Gerrit-Change-Number: 84194 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Bao Zheng (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84195?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... soc/amd/cezanne: Add an option to enable A/B recovery scheme Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable/disable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 05 Sep '24

05 Sep '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... mb/google/dedede/var/beadrix: Add LTE only daughterboard support Add FW_CONFIG for no port LTE skus. BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84232/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c index 131cb96..2662e36 100644 --- a/src/mainboard/google/dedede/variants/beadrix/gpio.c +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -122,7 +122,8 @@ static void fw_config_handle(void *unused) { - if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE))) + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) && + !fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE))) gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 0554baf..0c911e0 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -141,6 +141,7 @@ register "enable_delay_ms" = "20" device usb 3.3 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end @@ -239,6 +240,7 @@ register "reg_irq_cfg2" = "0x00" device i2c 28 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end # I2C 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Update touchscreen power sequence
by Eric Lai (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Tongtong Pan. Eric Lai has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/84196?usp=email ) Change subject: mb/google/dedede/var/awasuki: Update touchscreen power sequence ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: any spec change? -- To view, visit https://review.coreboot.org/c/coreboot/+/84196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Gerrit-Change-Number: 84196 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 01:36:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 05 Sep '24

05 Sep '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84231?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... mb/google/dedede/var/beadrix: Add LTE only daughterboard support Add FW_CONFIG for no port LTE skus, and probe 1A port in devicetree to match program.star config BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/84231/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d..d0ed6f1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -10,6 +10,7 @@ option DB_PORTS_1C 7 option DB_PORTS_1A_HDMI_LTE 8 option DB_PORTS_LTE 9 + option DB_PORTS_1A 10 end field STYLUS 4 option STYLUS_ABSENT 0 diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c index 131cb96..2662e36 100644 --- a/src/mainboard/google/dedede/variants/beadrix/gpio.c +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -122,7 +122,8 @@ static void fw_config_handle(void *unused) { - if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE))) + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) && + !fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE))) gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 0554baf..0c911e0 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -141,6 +141,7 @@ register "enable_delay_ms" = "20" device usb 3.3 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end @@ -239,6 +240,7 @@ register "reg_irq_cfg2" = "0x00" device i2c 28 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end # I2C 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84231 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 98: (2 comments) File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/3b540807_711b5e10?us… : PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB) > can we have a PTL SoC that can decide to drop PCD P2SB support if not then I would default select io […] I am not familiar with this but start looking into this. File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/c2db7088_217bcf46?us… : PS23, Line 56: 0xBAC > > Subrata, should we have soc/tcss. […] Subrata, I browsed across the ASL files and check how the Field under OperationRegion are written, the Offset always uses with direct value instead of macros. I assume you mean all the hard-coded offset value and not just this particular one. Unless the same offset has been used in multiple places, I'd rather leave it as it for consistency reason. In addition, the ASL will look closer to its converted .dsl file from the platform for debug/comparison purpose. Will it be okay? -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 98 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 00:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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coreboot-gerrit September 2024