coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 68: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83789/comment/54370d2f_4e7914c2?us… : PS47, Line 10: supporting ACPI ASL > will make the change in the next patchset. Done https://review.coreboot.org/c/coreboot/+/83789/comment/f968c98b_2ad58f2f?us… : PS47, Line 21: Verified > will add more info in the next patchset. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 68 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Sep 2024 00:28:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Hello Anil Kumar K, Bora Guvendik, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83789?usp=email to look at the new patch set (#69). Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... soc/intel/ptl: Add GPIOs for Panther Lake SOC Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b --- M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/gpio.c A src/soc/intel/pantherlake/include/soc/gpio.h A src/soc/intel/pantherlake/include/soc/gpio_defs.h A src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h 5 files changed, 1,057 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83789/69 -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 69 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Jérémy Compostella (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/5cbdb6f7_11c4b308?us… : PS13, Line 23: The issue addressed by this commit can be observed with the following : experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to : 0x400000 (4 MB). > This isn't a real issue, it's just a hypothesis that CONFIG\_DCACHE\_RAM\_SIZE is larger than the way size. The coreboot enhanced NEM code allows `CONFIG_DCACHE_RAM_SIZE` requiring multiple ways but it violate the Alder Lake, Meteor Lake and Panther Lake specification if such a configuration is used ⇒ the code is wrong and this is the issue these CL are addressing. These CL address a coreboot Intel eNEM code issue not a Google board issue. If you believe that `CONFIG_DCACHE_RAM_SIZE` should never be larger than the effective way size, then why does the bootblock eNEM support multiple ways ? And why is violating the specification by not considering the effective way size ? If you refuse the code to be fixed arguing that no configuration is taking advantage of it, please implement a mechanism in bootblock limiting the configuration to one **effective** way and remove the support for multiple ways. My only objective here is to fix code that does not comply with the specification and I was able to verify the code does not work by tweaking the configuration. *I tweaked the configuration, not the code*. My experiments demonstrated that 4MB works like a charm only with these two CLs. -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 Sep 2024 00:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 98: (1 comment) File src/soc/intel/pantherlake/acpi/pcie.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/ec3cdc96_c95daf15?us… : PS81, Line 269: Device (RP11) : { : Name (_ADR, 0x00060002) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : : Device (RP12) : { : Name (_ADR, 0x00060003) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } > don't you need SoC Kconfig guard for PTL-H that has 10 PCIe RPs? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 98 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 00:13:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Cliff Huang has uploaded a new patch set (#98) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... soc/intel/ptl: Add SoC ACPI directory for Panther Lake List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl A src/soc/intel/pantherlake/acpi/gpio.asl A src/soc/intel/pantherlake/acpi/hda.asl A src/soc/intel/pantherlake/acpi/pcie.asl A src/soc/intel/pantherlake/acpi/serialio.asl A src/soc/intel/pantherlake/acpi/southbridge.asl A src/soc/intel/pantherlake/acpi/tcss.asl A src/soc/intel/pantherlake/acpi/tcss_dma.asl A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl A src/soc/intel/pantherlake/acpi/tcss_xhci.asl A src/soc/intel/pantherlake/acpi/xhci.asl 13 files changed, 2,924 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/98 -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 98 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: make same cpu pyhsical address
by Wonkyu Kim (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, Wonkyu Kim. Hello Cliff Huang, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84230?usp=email to look at the new patch set (#2). Change subject: make same cpu pyhsical address ...................................................................... make same cpu pyhsical address 2 funtions are used to get cpu physical address like below. cpu_phys_address_size soc_phys_address_size And If CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH is defined, it can return different address size like below example) coreboot log: CPU physical address size: 46 bits OS log : DMAR: Host address width 42 So, need to make one API to use same physical address. BUG: none TEST: Check same address size in coreboot log and OS log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 --- M src/acpi/acpi_dmar.c M src/arch/x86/cpu_common.c M src/device/pci_device.c M src/include/cpu/cpu.h M src/soc/intel/common/block/systemagent/systemagent.c 5 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84230/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 Gerrit-Change-Number: 84230 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 68: (1 comment) File src/soc/intel/pantherlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/83789/comment/df39c3be_8bc14830?us… : PS49, Line 436: Name (JTAG, Package (0x02) > > I have asked our kernel pinctrl owner and we cannot skip PADs within a group, so if any of PADs ne […] Add a TODO task in cros bug: PTL SOC Code Cleanup https://partnerissuetracker.corp.google.com/issues/357011633#comment16 -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 68 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 05 Sep 2024 23:44:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: make same cpu pyhsical address
by Wonkyu Kim (Code Review) 05 Sep '24

05 Sep '24

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84230?usp=email ) Change subject: make same cpu pyhsical address ...................................................................... make same cpu pyhsical address 2 funtions are used to get cpu physical address like below. cpu_phys_address_size soc_phys_address_size And If CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH is defined, it can return different address size like below example) CB log : CPU physical address size: 46 bits OS log : DMAR: Host address width 42 So, need to make one API to use same physical address. BUG: none TEST: Check same address size in Coreboot log and OS log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 --- M src/acpi/acpi_dmar.c M src/arch/x86/cpu_common.c M src/device/pci_device.c M src/include/cpu/cpu.h M src/soc/intel/common/block/systemagent/systemagent.c 5 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84230/1 diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 67bca55..9725f2f 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -28,7 +28,7 @@ header->length = sizeof(acpi_dmar_t); header->revision = get_acpi_table_revision(DMAR); - dmar->host_address_width = soc_phys_address_size() - 1; + dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags; current = acpi_fill_dmar(current); diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 5f7cd5d..ddedea4 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -47,6 +47,9 @@ unsigned int cpu_phys_address_size(void) { + if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH) + return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH; + if (!(cpu_have_cpuid())) return 32; @@ -61,14 +64,6 @@ return 32; } -unsigned int soc_phys_address_size(void) -{ - if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH) - return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH; - - return cpu_phys_address_size(); -} - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a2ad2b3..859f085 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -578,7 +578,7 @@ /* Initialize 64-bit memory resource constraints above 4G. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); res->base = 4ULL * GiB; - res->limit = (1ULL << soc_phys_address_size()) - 1; + res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 5f32720..9783976 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -10,7 +10,6 @@ uintptr_t cpu_get_lapic_addr(void); struct bus; unsigned int cpu_phys_address_size(void); -unsigned int soc_phys_address_size(void); #if ENV_RAMSTAGE #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver"))) diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8d7432..a45f00d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -323,7 +323,7 @@ uint64_t touud; sa_read_map_entry(pcidev_path_on_root(SA_DEVFN_ROOT), &sa_memory_map[SA_TOUUD_REG], &touud); - const uint64_t len = POWER_OF_2(soc_phys_address_size()) - touud; + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; const char *scope = acpi_device_path(dev); acpigen_write_scope(scope); -- To view, visit https://review.coreboot.org/c/coreboot/+/84230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 Gerrit-Change-Number: 84230 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[S] Change in coreboot[main]: nb/intel/sandybridge: Add Kconfig to set default IGD allocation
by Matt DeVillier (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Angel Pons. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84225?usp=email ) Change subject: nb/intel/sandybridge: Add Kconfig to set default IGD allocation ...................................................................... Patch Set 4: (2 comments) File src/northbridge/intel/sandybridge/Kconfig: https://review.coreboot.org/c/coreboot/+/84225/comment/1cc097f4_35aa46c3?us… : PS3, Line 188: (CMOS-backed) > The fallback value is used whenever the option backend cannot retrieve the stored value in the backe […] Acknowledged https://review.coreboot.org/c/coreboot/+/84225/comment/74d0da0f_736eac7a?us… : PS3, Line 204: IGD_DEFAULT_INT_VALUE > I feel this name is too confusing, but I am currently too tired to come up with a better name. is IGD_DEFAULT_UMA_INDEX better? -- To view, visit https://review.coreboot.org/c/coreboot/+/84225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Gerrit-Change-Number: 84225 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 22:26:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: libpayload: add more condition to check valid PCI device id
by Wonkyu Kim (Code Review) 05 Sep '24

05 Sep '24

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84229?usp=email ) Change subject: libpayload: add more condition to check valid PCI device id ...................................................................... libpayload: add more condition to check valid PCI device id Checking more conditions to check valid PCI device id to avoid device stuck issue. Below are invalid PCI device id cases VID: 0x0 or 0xffff DID: 0x0 or 0xffff Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I772c4199c7a6c13a25590a36f1bfee17c1a44daf --- M payloads/libpayload/drivers/usb/usbinit.c 1 file changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84229/1 diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index a234b00..dfcdae9 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -116,15 +116,36 @@ return 0; } +static bool is_valid_pci_dev(int bus, int dev, int fun) +{ + u32 id; + u16 vid, did; + pcidev_t pci_device = PCI_DEV(bus, dev, fun); + + id = pci_read_config32(pci_device, REG_VENDOR_ID); + vid = id & 0xffff; + did = (id >> 16) & 0xffff; + + if ((vid == 0x0000) || (vid == 0xffff) || + (did == 0xffff) || (did== 0x0000)) { + usb_debug("PCI dev %02x:%02x:%02x [0x%04x|0x%04x] is not valid\n", + bus, dev, fun, vid, did); + return false; + } + return true; +} + static void usb_scan_pci_bus(int bus) { int dev, func; + + usb_debug("usb_scan_pci_bus start\n"); for (dev = 0; dev < 32; dev++) { u8 header_type; pcidev_t pci_device = PCI_DEV(bus, dev, 0); - /* Check if there's a device here at all. */ - if (pci_read_config32(pci_device, REG_VENDOR_ID) == 0xffffffff) + /* Check valid pci device*/ + if ( is_valid_pci_dev(bus, dev, 0) == false ) continue; /* @@ -143,6 +164,11 @@ for (; func >= 0; func--) { pci_device = PCI_DEV(bus, dev, func); + + /* Check valid pci device*/ + if ( is_valid_pci_dev(bus, dev, func) == false ) + continue; + header_type = pci_read_config8(pci_device, REG_HEADER_TYPE); /* If this is a bridge, scan the other side. */ if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == @@ -157,6 +183,7 @@ usb_controller_initialize(bus, dev, func); } } + usb_debug("usb_scan_pci_bus end\n"); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84229?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I772c4199c7a6c13a25590a36f1bfee17c1a44daf Gerrit-Change-Number: 84229 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com>

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