Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84225?usp=email )
Change subject: nb/intel/sandybridge: Add Kconfig to set default IGD allocation
......................................................................
nb/intel/sandybridge: Add Kconfig to set default IGD allocation
Add a Kconfig choice to select the default IGD memory allocation, for
users/ boards which do not use an option table to set it.
TEST=build/boot google/link, verify IGD size changes with selection.
Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/early_init.c
2 files changed, 31 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/84225/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index fa40b06..7c8dba3 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -180,4 +180,32 @@
config PRERAM_CBFS_CACHE_SIZE
default 0x0
+choice
+ prompt "Default IGD Memory Allocation"
+ default IGD_DEFAULT_SIZE_32MB
+ help
+ The amount of system memory allocated for the integrated GPU if not
+ set via a (CMOS-backed) option table.
+
+config IGD_DEFAULT_SIZE_32MB
+ bool "32MB"
+
+config IGD_DEFAULT_SIZE_64MB
+ bool "64MB"
+
+config IGD_DEFAULT_SIZE_96MB
+ bool "96MB"
+
+config IGD_DEFAULT_SIZE_128MB
+ bool "128MB"
+
+endchoice
+
+config IGD_DEFAULT_INT_VALUE
+ int
+ default 0 if IGD_DEFAULT_SIZE_32MB
+ default 1 if IGD_DEFAULT_SIZE_64MB
+ default 2 if IGD_DEFAULT_SIZE_96MB
+ default 3 if IGD_DEFAULT_SIZE_128MB
+
endif
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index a5ebf9d..60798f0 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -86,9 +86,10 @@
printk(BIOS_DEBUG, "Initializing Graphics...\n");
- /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */
- gfxsize = get_uint_option("gfx_uma_size", 0);
+ /* Fall back to IGD_DEFAULT_INT_VALUE for IGD memory */
+ gfxsize = get_uint_option("gfx_uma_size", IGD_DEFAULT_INT_VALUE);
+ /* Program IGD memory allocation by setting GGC[7:3] */
reg16 = pci_read_config16(HOST_BRIDGE, GGC);
reg16 &= ~0x00f8;
reg16 |= (gfxsize + 1) << 3;
--
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Gerrit-Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f
Gerrit-Change-Number: 84225
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Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu.
Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#11).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 96 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/11
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Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82729?usp=email )
Change subject: soc/intel/mtl: Hook up GMA ACPI brightness controls
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/82729/comment/4a84251f_b40a6104?us… :
PS2, Line 398: INTEL_GMA_BCLV_OFFSET
> I'm curious, where exactly are these backlight offset configs used? Are there any subsequent changes […]
I've added CB:84224 to use it for system76/mtl.
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Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/83696?usp=email )
Change subject: mb/system76/mtl: darp10: Add TCSS configs
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/system76/mtl/variants/darp10/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83696/comment/ab17a035_04983b18?us… :
PS1, Line 10: BIT 6 is orientational
> So it’s 0 below in 0x82. […]
This is an enable/disable bit. I don't know what enabling it actually does.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84199?usp=email )
Change subject: soc/intel/common/systemagent: Fix grammer in comments
......................................................................
soc/intel/common/systemagent: Fix grammer in comments
Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199
Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/common/block/systemagent/systemagent.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Nicholas Chin: Looks good to me, approved
Shuo Liu: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e8d7432..6239a46 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -274,7 +274,7 @@
int index = 0;
/**
- * If SoC has multiple PCIe domains, only reading resources from the first one.
+ * If SoC has multiple PCIe domains, only read resources from the first one.
*/
if (!is_dev_on_domain0(dev))
return;
--
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Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83410?usp=email )
Change subject: mb/google/puff: Use auto fan control
......................................................................
Abandoned
dropping as this seems to cause issues on some puff devices
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