coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Michał Żygowski (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons, Felix Held. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email ) Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80318/comment/f48ca8e3_4ca246f5?us… : PS6, Line 7: util/superiotool/ite: Add extra dumps for IT8613E EC > I believe they have access to the datasheet under NDA with the vendor. […] Yes, it is non-public spec. Added info to commit message. https://review.coreboot.org/c/coreboot/+/80318/comment/14521a86_93f71bbe?us… : PS6, Line 14: briodge > typo: bridge Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 05 Sep 2024 10:49:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Michał Żygowski (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Angel Pons, Felix Held, Michał Żygowski. Hello Angel Pons, Felix Held, Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80318?usp=email to look at the new patch set (#7). Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... util/superiotool/ite: Add extra dumps for IT8613E EC IT8613E EC space is divided into 3 banks selectable by EC index 0x06 bits 6:5. Bank0 mostly contains the ITE EC registers known by coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature reading registers. Bank2, however, contains additional registers used to select the temperature source reported in TMPIN reading registers, PECI bridge registers as well as FAN2-5 controls and extra vectors. Dump the additional banks using extra-selectors. Based on non-public IT8613E Preliminary Specification V0.3. TEST=Perform the IT8613E dump on Hardkernel ODROID H4+. Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/superiotool/ite.c 1 file changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/80318/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 22: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/d5a694fa_b3ce2074?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > > Subrata - the boot time increase was not consistently coming in 15:starting LZMA decompress (ignor […] Got it - my experiments were with pl4 = 19 and pl4 = 23 for 65 watts adaptors and the observations were not consistent .I will check with a larger difference in PL4 and get back to you with observation and then continue with RCA -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 10:19:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 96: (1 comment) File src/soc/intel/pantherlake/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/f3ca125d_855a659f?us… : PS23, Line 5: INTC1041 > Hi, I have added the dptf.h in include/soc directory. Removed using dptf.asl. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 96 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 10:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 86: (5 comments) Patchset: PS81: > @mishra.saurabh@intel.com, can you please ensure you are following CB:84182 and CB:84183 while creating ramstage CL for panther lake? Also, CB:84217 and CB:84220 File src/soc/intel/pantherlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/83798/comment/c03367eb_2ee1fec7?us… : PS50, Line 15: > I am checking this data from PNP team. ping, if this is good time to check this ? File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/ef4164a5_6a1c68bf?us… : PS71, Line 140: > Yes. The code is ready once GPE1 changes CLs are merged, I will work with […] Acknowledged File src/soc/intel/pantherlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/83798/comment/11f79fe1_a5fd4f20?us… : PS71, Line 110: > Yes. The code is ready once GPE1 changes CLs are merged, I will work with […] Acknowledged File src/soc/intel/pantherlake/retimer.c: https://review.coreboot.org/c/coreboot/+/83798/comment/aa49213d_260e592a?us… : PS71, Line 19: : for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { > Hi, declaring variables of the same type together in for loop is accepted in c. > Here, variable i is "uint8_t " type, while ec_port variable is declared "int". > This will give an error since mixing types in the initialization section is not allowed. > > Can be used as below? > ```` > for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) { > ```` sure -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 86 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 10:01:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 86: (2 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/4bf0e957_fe990727?us… : PS75, Line 381: config DROP_CPU_FEATURE_PROGRAM_IN_FSP keep this by making `default n` File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/92081e68_64bf3129?us… : PS37, Line 30: C_STATE_C0, /* 0 */ : C_STATE_C1, /* 1 */ : C_STATE_C1E, /* 2 */ : C_STATE_C6_SHORT_LAT, /* 3 */ : C_STATE_C6_LONG_LAT, /* 4 */ : C_STATE_C7_SHORT_LAT, /* 5 */ : C_STATE_C7_LONG_LAT, /* 6 */ : C_STATE_C7S_SHORT_LAT, /* 7 */ : C_STATE_C7S_LONG_LAT, /* 8 */ : C_STATE_C8, /* 9 */ : C_STATE_C9, /* 10 */ : C_STATE_C10, /* 11 */ : NUM_C_STATES > I will come back with the data, checking Internally with c states owner. ping! is this a good time to check ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 86 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 09:59:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 22: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/8bc70074_5b7c4a8d?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > Subrata - the boot time increase was not consistently coming in 15:starting LZMA decompress (ignore for x86) -- after starting to load payload > 1050:finished reading kernel from disk > So i could not root cause sorry I'm unable to follow your statement. If you're saying that boot time has regressed after limiting PL4 at a certain level, then there must be an explanation. Often, we've seen boot time regress because the CPU is operating at low speed, the clock has been reduced, or there's an idle delay. I'm asking you to narrow down the observation by looking at the factors that become prevalent when you limit PL4. Otherwise, this is just another observation without a root cause. -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 09:57:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek: Remove redundant struct pad_func and PAD_* definitions
by Yidi Lin (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84222?usp=email ) Change subject: soc/mediatek: Remove redundant struct pad_func and PAD_* definitions ...................................................................... soc/mediatek: Remove redundant struct pad_func and PAD_* definitions Clean up redundant `struct pad_func` and `PAD_*` definitions. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/common/flash_controller.c M src/soc/mediatek/common/include/soc/flash_controller_common.h M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/spi.c M src/soc/mediatek/mt8186/i2c.c M src/soc/mediatek/mt8186/spi.c M src/soc/mediatek/mt8188/i2c.c M src/soc/mediatek/mt8188/spi.c M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/spi.c M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/pcie.c M src/soc/mediatek/mt8195/spi.c M src/soc/mediatek/mt8196/i2c.c M src/soc/mediatek/mt8196/spi.c 17 files changed, 23 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/84222/1 diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index 5091dcc..ddeb537 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -9,13 +9,6 @@ #include "gpio.h" -struct pad_func { - u8 pin_id; - u8 func; -}; - -#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} - static void nor_set_gpio_pinmux(void) { const struct pad_func *ptr = NULL; @@ -30,9 +23,8 @@ ptr = nor_pinmux; for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { - gpio_set_pull((gpio_t){.id = ptr[i].pin_id}, - GPIO_PULL_ENABLE, GPIO_PULL_UP); - gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode(ptr[i].gpio, ptr[i].func); } } diff --git a/src/soc/mediatek/common/flash_controller.c b/src/soc/mediatek/common/flash_controller.c index 4eaa37d..4f0d4b0 100644 --- a/src/soc/mediatek/common/flash_controller.c +++ b/src/soc/mediatek/common/flash_controller.c @@ -224,20 +224,20 @@ return 0; } -int mtk_snfc_init_pad_func(const struct mtk_snfc_pad_func *pad_func, enum gpio_drv strength) +int mtk_snfc_init_pad_func(const struct pad_func *pad, enum gpio_drv strength) { - gpio_set_pull(pad_func->gpio, GPIO_PULL_ENABLE, pad_func->select); - gpio_set_mode(pad_func->gpio, pad_func->func); + gpio_set_pull(pad->gpio, GPIO_PULL_ENABLE, pad->select); + gpio_set_mode(pad->gpio, pad->func); - if (gpio_set_driving(pad_func->gpio, strength) < 0) { + if (gpio_set_driving(pad->gpio, strength) < 0) { printk(BIOS_ERR, "%s: failed to set pin drive to %d for %d\n", - __func__, strength, pad_func->gpio.id); + __func__, strength, pad->gpio.id); return -1; } printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__, - gpio_get_driving(pad_func->gpio)); + gpio_get_driving(pad->gpio)); return 0; } diff --git a/src/soc/mediatek/common/include/soc/flash_controller_common.h b/src/soc/mediatek/common/include/soc/flash_controller_common.h index c71ae17..69ff3c7 100644 --- a/src/soc/mediatek/common/include/soc/flash_controller_common.h +++ b/src/soc/mediatek/common/include/soc/flash_controller_common.h @@ -76,13 +76,7 @@ }; check_member(mtk_nor_regs, fdma_end_dadr, 0x724); -struct mtk_snfc_pad_func { - gpio_t gpio; - u8 func; - enum pull_select select; -}; - int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); -int mtk_snfc_init_pad_func(const struct mtk_snfc_pad_func *pad_func, enum gpio_drv strength); +int mtk_snfc_init_pad_func(const struct pad_func *pad, enum gpio_drv strength); #endif /* __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ */ diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 870dac5..2fc850a 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -50,6 +50,16 @@ uint8_t width; }; +struct pad_func { + gpio_t gpio; + u8 func; + enum pull_select select; +}; + +#define PAD_FUNC(name, func) { GPIO(name), PAD_##name##_FUNC_##func } +#define PAD_FUNC_GPIO(name) { GPIO(name), 0 } +#define PAD_FUNC_SEL(name, func, sel) { GPIO(name), PAD_##name##_FUNC_##func, sel } + void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 8bd7c36..ec7c169 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -53,13 +53,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 9404f93..2105d26 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -35,14 +35,6 @@ } }; -struct pad_func { - u8 pin_id; - u8 func; -}; - -#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} -#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} - static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPI_MI, SPI0_MI), @@ -100,7 +92,7 @@ ptr = bus1_pad1_funcs; } for (int i = 0; i < 4; i++) - gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + gpio_set_mode(ptr[i].gpio, ptr[i].func); } const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c index 9e7e4b3..d33fdad 100644 --- a/src/soc/mediatek/mt8186/i2c.c +++ b/src/soc/mediatek/mt8186/i2c.c @@ -58,13 +58,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { [0] = { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index adbd437..9f912ad 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -41,16 +41,6 @@ } }; -struct pad_func { - gpio_t gpio; - u8 func; - enum pull_select select; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func, GPIO_PULL_DOWN} -#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} -#define PAD_FUNC_GPIO(name) {GPIO(name), 0, GPIO_PULL_DOWN} - static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPI0_MI, SPI0_MI_A), diff --git a/src/soc/mediatek/mt8188/i2c.c b/src/soc/mediatek/mt8188/i2c.c index 1de37c5..5d5ba37 100644 --- a/src/soc/mediatek/mt8188/i2c.c +++ b/src/soc/mediatek/mt8188/i2c.c @@ -53,13 +53,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { [0] = { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8188/spi.c b/src/soc/mediatek/mt8188/spi.c index 0596bb9..2e7052f 100644 --- a/src/soc/mediatek/mt8188/spi.c +++ b/src/soc/mediatek/mt8188/spi.c @@ -41,16 +41,6 @@ }, }; -struct pad_func { - gpio_t gpio; - u8 func; - enum pull_select select; -}; - -#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} -#define PAD_FUNC_GPIO(name) {GPIO(name), 0} - static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPIM0_MISO, SPIM0_MISO), diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index a3f236a..a044b184 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -66,13 +66,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { [0] = { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index 42e5b4a..45e941f 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -42,14 +42,6 @@ } }; -struct pad_func { - u8 pin_id; - u8 func; -}; - -#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} -#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} - static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPI0_MI, SPI0_A_MI), @@ -109,7 +101,7 @@ ptr = pad0_funcs[bus]; for (int i = 0; i < 4; i++) - gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + gpio_set_mode(ptr[i].gpio, ptr[i].func); } static const struct spi_ctrlr spi_flash_ctrlr = { diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c index e404107..e49f1f9 100644 --- a/src/soc/mediatek/mt8195/i2c.c +++ b/src/soc/mediatek/mt8195/i2c.c @@ -53,13 +53,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { [0] = { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 2676207..1c93d46 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -10,13 +10,6 @@ #define PCIE_REG_BASE_PORT0 0x112f0000 -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func pcie_pins[2][3] = { { PAD_FUNC(PCIE_WAKE_N, WAKEN), diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index 98b0d54..016cc29 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -34,14 +34,6 @@ }, }; -struct pad_func { - u8 pin_id; - u8 func; -}; - -#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} -#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} - static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPIM0_MI, SPIM0_MI), @@ -89,7 +81,7 @@ ptr = pad0_funcs[bus]; for (int i = 0; i < 4; i++) - gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + gpio_set_mode(ptr[i].gpio, ptr[i].func); } static const struct spi_ctrlr spi_flash_ctrlr = { diff --git a/src/soc/mediatek/mt8196/i2c.c b/src/soc/mediatek/mt8196/i2c.c index 94e3c3f..3a2f9ed 100644 --- a/src/soc/mediatek/mt8196/i2c.c +++ b/src/soc/mediatek/mt8196/i2c.c @@ -93,13 +93,6 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, "Wrong size of mtk_i2c_bus_controller"); -struct pad_func { - gpio_t gpio; - u8 func; -}; - -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} - static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { [0] = { PAD_FUNC(SDA0, SDA0), diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c index 09cd073..1a760e7 100644 --- a/src/soc/mediatek/mt8196/spi.c +++ b/src/soc/mediatek/mt8196/spi.c @@ -12,9 +12,7 @@ #include <soc/spi.h> #include <spi_flash.h> -#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} - -static const struct mtk_snfc_pad_func nor_pinmux[4] = { +static const struct pad_func nor_pinmux[4] = { PAD_FUNC_SEL(SDA10, SF_CK, GPIO_PULL_DOWN), PAD_FUNC_SEL(SCL10, SF_CS, GPIO_PULL_UP), PAD_FUNC_SEL(PERIPHERAL_EN5, SF_D0, GPIO_PULL_DOWN), -- To view, visit https://review.coreboot.org/c/coreboot/+/84222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Gerrit-Change-Number: 84222 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
by Yidi Lin (Code Review) 05 Sep '24

05 Sep '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84221?usp=email ) Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h ...................................................................... soc/mediatek/common: Move common GPIO definitions to gpio_defs.h BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- A src/soc/mediatek/common/include/soc/gpio_defs.h M src/soc/mediatek/mt8186/include/soc/gpio.h M src/soc/mediatek/mt8188/include/soc/gpio.h M src/soc/mediatek/mt8192/include/soc/gpio.h M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8196/include/soc/gpio.h 6 files changed, 49 insertions(+), 179 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/84221/1 diff --git a/src/soc/mediatek/common/include/soc/gpio_defs.h b/src/soc/mediatek/common/include/soc/gpio_defs.h new file mode 100644 index 0000000..3b0ddea --- /dev/null +++ b/src/soc/mediatek/common/include/soc/gpio_defs.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_GPIO_DEFS_H +#define SOC_MEDIATEK_COMMON_GPIO_DEFS_H + +#include <types.h> + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index 4ce1e98..1c1f148 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -10,41 +10,13 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 185 -enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - #define GPIO_ID(name) PAD_##name##_ID -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - enum { PIN(0, EINT0, 0, 13, 0x16, 0x50, I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0, @@ -603,13 +575,6 @@ RES5, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { struct val_regs dir[7]; uint8_t rsv00[144]; diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h index 916cf84..4e666f1 100644 --- a/src/soc/mediatek/mt8188/include/soc/gpio.h +++ b/src/soc/mediatek/mt8188/include/soc/gpio.h @@ -10,40 +10,12 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 177 enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, GPIO00, 0, 6, 0x31, 0xe0, TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK, I2SIN_MCK, I2SO2_MCK, DBG_MON_A0), @@ -577,12 +549,6 @@ RES5, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; struct gpio_regs { struct val_regs dir[7]; uint8_t rsv00[144]; diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h index 716a63d..4b95f87 100644 --- a/src/soc/mediatek/mt8192/include/soc/gpio.h +++ b/src/soc/mediatek/mt8192/include/soc/gpio.h @@ -5,38 +5,10 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, EINT0, 0, 9, 0x23, 0xb0, SPI6_CLK, I2S5_MCK, PWM_0, TDM_LRCK, TP_GPIO0_AO, MD_INT0, RES7), @@ -699,13 +671,6 @@ I2S6_DI, I2S8_DI, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { struct val_regs dir[7]; uint8_t rsv00[144]; diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 02c3580..1da8b55 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -5,38 +5,10 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, GPIO_00, 1, 0, 0x23, 0x60, TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0, PERSTN_1, IDDIG_1P, DMIC4_CLK), @@ -470,13 +442,6 @@ RES5, RES6, DBG_MON_A13), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { struct val_regs dir[7]; uint8_t rsv00[144]; diff --git a/src/soc/mediatek/mt8196/include/soc/gpio.h b/src/soc/mediatek/mt8196/include/soc/gpio.h index a60cba6..0981a0b 100644 --- a/src/soc/mediatek/mt8196/include/soc/gpio.h +++ b/src/soc/mediatek/mt8196/include/soc/gpio.h @@ -10,23 +10,11 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 271 -enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { struct val_regs dir[16]; struct val_regs dout[16]; @@ -35,29 +23,6 @@ uint32_t dram_pinmux_trapping; }; -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - enum { PIN(0, EINT0, 0, 0, 0x18, 0xa0, DMIC1_CLK, RES2, SPI3_A_MO, FMI2S_B_LRCK, -- To view, visit https://review.coreboot.org/c/coreboot/+/84221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Gerrit-Change-Number: 84221 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 22: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/bda27084_eaca0f27?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > > 1) Setting PL4 as 9 which is the PL4 value for 30watts is increasing boot time significantly (more […] Subrata - the boot time increase was not consistently coming in 15:starting LZMA decompress (ignore for x86) -- after starting to load payload 1050:finished reading kernel from disk So i could not root cause sorry -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 22 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 09:38:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit September 2024