coreboot-gerrit September 2024

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PSYS setting
by Shon Wang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik. Shon Wang has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: Add PSYS setting ...................................................................... Patch Set 15: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83593/comment/a0435d42_60464c8c?us… : PS14, Line 11: voltage by > Just one space please. Done File src/mainboard/google/brya/variants/bujia/ramstage.c: https://review.coreboot.org/c/coreboot/+/83593/comment/fc4988d1_49ec947d?us… : PS14, Line 5: #include <device/device.h> : #include <device/pci_ids.h> : #include <device/pci_ops.h> > do you need these 3? Done https://review.coreboot.org/c/coreboot/+/83593/comment/1881bbbf_daca8d32?us… : PS14, Line 52: type-c > Type-C Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 15 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Sep 2024 08:29:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PSYS setting
by Shon Wang (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Shon Wang, Subrata Banik. Hello Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83593?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Derek Huang, Verified+1 by build bot (Jenkins) Change subject: mb/google/brask/var/bujia: Add PSYS setting ...................................................................... mb/google/brask/var/bujia: Add PSYS setting According to the Intel OPS spec, the DC power from display is 12~19V@8A max. It can't set PsysPmax by unknown voltage, so get voltage by ec command "ectool adcread 4" then calculate PsysPmax value. The OPS display can supply 90W power, configure psys_pl2 to limit the system power to 90W. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W. Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/bujia/Makefile.mk A src/mainboard/google/brya/variants/bujia/ramstage.c 2 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 15 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 10: (5 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/0e55102a_af90fc4c?us… : PS3, Line 406: pmc_clear_gpi_gpe0_status > > Subrata, […] Acknowledged File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/187ee586_e17484a7?us… : PS10, Line 296: : /* GPE */ : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a) : { : return NULL; : } : : /* disable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask) : { : } : : /* enable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask) : { : } move this _weak implementation the file beginning and a comment saying `/* SoC overrides for GPE1 when `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` enabled */ ? https://review.coreboot.org/c/coreboot/+/84104/comment/fb29d48e_81a5488e?us… : PS10, Line 329: pmc_disable_gpe1 can you please move this API after `pmc_disable_gpe0`? https://review.coreboot.org/c/coreboot/+/84104/comment/40103227_686bb247?us… : PS10, Line 396: reset_std_gpe1_status move after `reset_std_gpe0_status` https://review.coreboot.org/c/coreboot/+/84104/comment/55dfb13e_634e1ca2?us… : PS10, Line 406: print_std_gpe1_sts move after `print_std_gpe0_sts`? -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 08:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 35 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 36b47a3..459a952 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -76,4 +76,16 @@ Define the slp_s0_residency frequency to be reported in the LPIT ACPI table. +config SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 + bool "Use GPE1 Event bits" + help + Include GPE1 STS and EN registers in FADT. Requires define GPE1_STS(0) + and GPE1_REG_MAX from the SOC header. The SOC needs to have GPE1 block + implemented to select this. This flag will also be used to determine the + standard GPE0/1 event methods to use in the ASL code or devicetree for the + internal wake capable devices. GPE1 Event Bit is an extension of GPE0 + (present in all Intel SoC platform). GPE1 Events include the power + management, hot plug, and PCIe events for the internal devices. Select + this Kconfig to support SoCs that publish GPE1 as part of PMC IO register. + endif diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 1faf433..dcd4dc4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -107,6 +107,16 @@ /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : 0; + if (fadt->gpe1_blk) { + fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t); + /* + * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets. + * gpe1_base is the starting bit offset for GPE1. + */ + fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8; + } + fill_fadt_extended_pm_io(fadt); fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fd61489..18d1b4d 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -8,6 +8,19 @@ #define PCH_PMC_EPOC 0x18EC +/* + * GPE1 support is introduced in PTL. The existing standard GPE + * functions will cover GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is + * selected. In addition, the following SOC GPE1 defines are required in common + * code but not present in older platform headers. Therefore, the dummy entries + * are added here for platforms without GPE1 support. + */ +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) +#define GPE1_STS(x) (0x0 + ((x) * 4)) +#define GPE1_EN(x) (0x0 + ((x) * 4)) +#define GPE1_REG_MAX 0 +#endif + /** * enum pch_pmc_xtal - External crystal oscillator frequency. * @XTAL_24_MHZ: 24 MHz external crystal. -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 15 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` option
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Ronak Kanabar, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84220?usp=email ) Change subject: drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` option ...................................................................... drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` option Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly improves the option's prompt and help text. TEST=Built and booted google/rex successfully. Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig 4 files changed, 7 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/84220/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index bbf0710..8e9dcdc 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -533,4 +533,11 @@ ChromeOS devices typically do not require the MBP information, hence it is disabled by default on ChromeOS. +config BUILDING_WITH_DEBUG_FSP + bool "Use Debug FSP for Build" + default n + help + Enable this option if you are using a debug build of the FSP (Firmware Support Package) + in your project. + endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c1cc993..2c441fc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -493,12 +493,6 @@ help Size of Descriptor Region in the FMAP -config BUILDING_WITH_DEBUG_FSP - bool "Debug FSP is used for the build" - default n - help - Set this option if debug build of FSP is used. - config INTEL_GMA_BCLV_OFFSET default 0xc8258 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 753af7c..b5c0bcf 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -380,12 +380,6 @@ hex default 0x800000 -config BUILDING_WITH_DEBUG_FSP - bool "Debug FSP is used for the build" - default n - help - Set this option if debug build of FSP is used. - config DROP_CPU_FEATURE_PROGRAM_IN_FSP bool default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index e5f7c92..98248fe 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -242,10 +242,4 @@ int default 16 -config BUILDING_WITH_DEBUG_FSP - bool "Debug FSP is used for the build" - default n - help - Set this option if debug build of FSP is used. - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Gerrit-Change-Number: 84220 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creation
by Subrata Banik (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Ronak Kanabar, Subrata Banik, Tarun. Hello Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Ronak Kanabar, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84217?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creation ...................................................................... drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creation This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling this option can improve boot time on platforms that do not utilize the MBP HOB, such as ChromeOS devices. The option is disabled by default on ChromeOS and enabled by default on other platforms. On ADL-P based platforms, this option is forced to be enabled as ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config from MTL and TGL config file. TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when it is disabled. Also verified that the system boots successfully in both cases. Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig 4 files changed, 16 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84217/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Gerrit-Change-Number: 84217 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Ren Kuo (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Ren Kuo has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 21: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 21 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 07:12:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Ren Kuo (Code Review) 05 Sep '24

05 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Ren Kuo has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 21: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 21 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 07:12:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Fix booting to kernel without battery
by Ren Kuo (Code Review) 05 Sep '24

05 Sep '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84219?usp=email ) Change subject: mb/google/brox/jubilant: Fix booting to kernel without battery ...................................................................... mb/google/brox/jubilant: Fix booting to kernel without battery Modify jubilant cpu power limit setting depend on the brox baseboad settgins: https://review.coreboot.org/c/coreboot/+/83752 BUG=b:364441688 BRANCH=None TEST=Able to successfully boot on jubilant photo SKU1 and SKU2 boards with 65W adaptors of cold boot. Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/ramstage.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84219/1 diff --git a/src/mainboard/google/brox/variants/jubilant/ramstage.c b/src/mainboard/google/brox/variants/jubilant/ramstage.c index 86418da..f4e0bcf 100644 --- a/src/mainboard/google/brox/variants/jubilant/ramstage.c +++ b/src/mainboard/google/brox/variants/jubilant/ramstage.c @@ -32,16 +32,6 @@ }, }; -const struct system_power_limits sys_limits[] = { - /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_RPL_P_ID_3, 15, 60 }, - { PCI_DID_INTEL_RPL_P_ID_4, 15, 60 }, -}; - -const struct psys_config psys_config = { - .efficiency = 86, -}; - void __weak variant_devtree_update(void) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); @@ -50,5 +40,4 @@ size_t limits_size = ARRAY_SIZE(performance_efficient_limits); variant_update_power_limits(limits, limits_size); - variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216 Gerrit-Change-Number: 84219 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: vm index changes as PTL vm entries are not con...
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83997?usp=email ) Change subject: soc/intel/common/gpio: vm index changes as PTL vm entries are not continuous ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Patchset: PS1: > blocking the code review due to https://review.coreboot.org/c/coreboot/+/83981/comments/74cb3b78_ddfadfc2 I'm taking back my -2 as i'm really running short of time to take PTL SoC code changes. I have requested Intel to share the doc at the earliest -- To view, visit https://review.coreboot.org/c/coreboot/+/83997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b Gerrit-Change-Number: 83997 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 05 Sep 2024 06:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit September 2024