coreboot-gerrit September 2024

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Bao Zheng (Code Review) 06 Sep '24

06 Sep '24

Hello Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84233?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Add combo new layout for new family ...................................................................... amdfwtool: Add combo new layout for new family The new layout definition has a new way to support combo. It packs multiple ISH entries into PSP L1 directory. TEST=Identical test on all AMD platform Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 22 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Bao Zheng (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Jason Glenesk, Marshall Dawson, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84195?usp=email to look at the new patch set (#4). Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... soc/amd/cezanne: Add an option to enable A/B recovery scheme Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to disable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Bao Zheng (Code Review) 06 Sep '24

06 Sep '24

Bao Zheng has restored this change. ( https://review.coreboot.org/c/coreboot/+/84233?usp=email ) Change subject: amdfwtool: Add combo new layout for new family ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: restore Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Matt DeVillier (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Jason Glenesk, Marshall Dawson, Zheng Bao. Matt DeVillier has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/5b7e316f_94271e39?us… : PS3, Line 22: /disable nit: based on the code change, it appears that 'no recovery' is the default, and the flag is passed to enable (but not disable) the A/B recovery scheme. -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 14:38:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by Angel Pons (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Alicja Michalska, David Milosevic, Felix Singer, Lean Sheng Tan. Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email ) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... Patch Set 4: Code-Review+1 (10 comments) Patchset: PS2: > i think we also support odroid-h4 plus too, should you add this as another variant? What are the differences? If possible I'd try to avoid creating variants (different firmware builds) and instead have the same coreboot target for H4, H4 plus and whatever File src/mainboard/hardkernel/odroid-h4/Kconfig: https://review.coreboot.org/c/coreboot/+/83979/comment/5d0806d3_081cff3b?us… : PS4, Line 37: config NO_POST : default y : There's a FFC (Flat Flexible Cable) connector on the bottom of the board named "ESPI_DEBUG1", so I would keep POST codes enabled in case someone needs them to debug. File src/mainboard/hardkernel/odroid-h4/bootblock.c: https://review.coreboot.org/c/coreboot/+/83979/comment/ecab88b1_2f372e70?us… : PS4, Line 13: ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10 What is GP10 used for? Seems unused on both schematics and in vendor firmware default settings (0x00, same as chip default). Please remove https://review.coreboot.org/c/coreboot/+/83979/comment/9c91ab83_738f1d21?us… : PS4, Line 14: ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31 GP31 is used as CTS# so this should be removed too https://review.coreboot.org/c/coreboot/+/83979/comment/84009726_e4393a4a?us… : PS4, Line 15: ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40 This seems to be used as PWRGD3, going to SYS_PWROK. I think this should be removed. https://review.coreboot.org/c/coreboot/+/83979/comment/360e260e_38a15045?us… : PS4, Line 16: Enable Pin GP50 This is not GP50 (doesn't appear in the schematics), but the value matches vendor firmware. File src/mainboard/hardkernel/odroid-h4/gpio.h: https://review.coreboot.org/c/coreboot/+/83979/comment/96b25019_e42b3db7?us… : PS4, Line 96: PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ This is not used File src/mainboard/hardkernel/odroid-h4/ramstage_fsp_params.c: PS4: No license header https://review.coreboot.org/c/coreboot/+/83979/comment/22b87964_407e1fa0?us… : PS4, Line 4: : fsp_s_config->PchLegacyIoLowLatency = 1; : fsp_s_config->PchDmiAspmCtrl = 0; Why? File src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/83979/comment/8463c89f_78647279?us… : PS4, Line 29: TODO: Implement __weak variant_is_half_populated(void) function. Copy-pasta? This board has no variants, so this doesn't make much sense -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 14:10:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/brox/variants/brox: remove PL4 value modification
by Sumeet R.P. (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Eric Lai, Karthik Ramasubramanian, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sumeet R.P. has posted comments on this change by Sumeet R.P.. ( https://review.coreboot.org/c/coreboot/+/83662?usp=email ) Change subject: mb/google/brox/variants/brox: remove PL4 value modification ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This change is available/ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d Gerrit-Change-Number: 83662 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 14:02:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67065?usp=email ) Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER ...................................................................... 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER Signing is performed with test keys by default, set CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys. Depending on the version of the Talos II firmware this alone might not allow booting because coreboot replaces only part of the stock firmware and its newer versions enable secure boot by default (not to be confused with SecureBoot in EFI). The signing performed in this commit is still a prerequisite and might as well be done on its own. Fixing operation with newer stock firmware will be done in a follow-up change. Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M .gitmodules A 3rdparty/open-power-signing-utils M Makefile.mk M src/soc/ibm/power9/Kconfig M src/soc/ibm/power9/Makefile.mk 5 files changed, 51 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/.gitmodules b/.gitmodules index eec69fd..c1d7849 100644 --- a/.gitmodules +++ b/.gitmodules @@ -65,3 +65,6 @@ [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"] path = src/vendorcode/amd/opensil/genoa_poc/opensil url = https://review.coreboot.org/opensil_genoa_poc.git +[submodule "3rdparty/open-power-signing-utils"] + path = 3rdparty/open-power-signing-utils + url = https://review.coreboot.org/open-power-signing-utils.git diff --git a/3rdparty/open-power-signing-utils b/3rdparty/open-power-signing-utils new file mode 160000 index 0000000..591c8f5 --- /dev/null +++ b/3rdparty/open-power-signing-utils @@ -0,0 +1 @@ +Subproject commit 591c8f53482243626901e1cc8a4ae321f314040d diff --git a/Makefile.mk b/Makefile.mk index 2b67947..a046438 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -679,6 +679,7 @@ CSE_FPT:=$(objutil)/cbfstool/cse_fpt CSE_SERGER:=$(objutil)/cbfstool/cse_serger ECCTOOL:=$(objutil)/ffs/ecc/ecc +CREATE_CONTAINER:=$(objutil)/open-power-signing-utils/create-container $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -726,6 +727,12 @@ cd $(objutil)/ffs && autoreconf -i && ./configure $(MAKE) -C $(objutil)/ffs +$(CREATE_CONTAINER): + @printf " Compile Open-Power SecureBoot Signing Utils\n" + cp -r $(top)/3rdparty/open-power-signing-utils $(objutil) + cd $(objutil)/open-power-signing-utils && autoreconf -i -Wno-unsupported && ./configure + $(MAKE) -C $(objutil)/open-power-signing-utils + APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py @@ -836,7 +843,7 @@ include util/crossgcc/Makefile.mk .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) $(CREATE_CONTAINER) ########################################################################### # Common recipes for all stages diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index 9f3323b..232beb7 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -10,5 +10,14 @@ This SoC is the minimal template working on POWER9 Talos II platform. if SOC_IBM_POWER9 - # nothing here yet + +config SIGNING_KEYS_DIR + string "Directory with OpenPower signing keys" + default "" + help + Specifies path to directory containing hw_key_{a,b,c}.key + and sw_key_p.key files (all in PEM format). Key name suffixes + correspond to options of create-container from OpenPower + Signing Utils. By default, test keys are used. + endif diff --git a/src/soc/ibm/power9/Makefile.mk b/src/soc/ibm/power9/Makefile.mk index f0ce2ea..b2aa581 100644 --- a/src/soc/ibm/power9/Makefile.mk +++ b/src/soc/ibm/power9/Makefile.mk @@ -14,9 +14,35 @@ ramstage-y += rom_media.c ramstage-y += timer.c -files_added:: $(obj)/coreboot.rom.ecc +ifeq ($(CONFIG_SIGNING_KEYS_DIR),"") + KEYDIR = $(top)/3rdparty/open-power-signing-utils/test/keys +else + KEYDIR = $(CONFIG_SIGNING_KEYS_DIR) +endif -$(obj)/coreboot.rom.ecc: $(obj)/coreboot.rom | $(ECCTOOL) - $(ECCTOOL) --inject $< --output $@ --p8 +PHONY += sign_and_add_ecc +sign_and_add_ecc: $(obj)/coreboot.rom | $(ECCTOOL) $(CREATE_CONTAINER) +ifeq ($(CONFIG_SIGNING_KEYS_DIR),"") + @printf " NOTE: signing firmware with test keys\n" +endif + @printf " SBSIGN $(subst $(obj)/,,$<)\n" + [ -e "$(KEYDIR)/hw_key_a.key" ] || ( echo "error: $(KEYDIR)/hw_key_a.key" is missing; exit 1 ) + [ -e "$(KEYDIR)/hw_key_b.key" ] || ( echo "error: $(KEYDIR)/hw_key_b.key" is missing; exit 1 ) + [ -e "$(KEYDIR)/hw_key_c.key" ] || ( echo "error: $(KEYDIR)/hw_key_c.key" is missing; exit 1 ) + [ -e "$(KEYDIR)/sw_key_p.key" ] || ( echo "error: $(KEYDIR)/sw_key_p.key" is missing; exit 1 ) + $(CREATE_CONTAINER) -a $(KEYDIR)/hw_key_a.key -b $(KEYDIR)/hw_key_b.key -c $(KEYDIR)/hw_key_c.key \ + -p $(KEYDIR)/sw_key_p.key --payload $(objcbfs)/bootblock.bin \ + --imagefile $(obj)/bootblock.signed + $(CREATE_CONTAINER) -a $(KEYDIR)/hw_key_a.key -b $(KEYDIR)/hw_key_b.key -c $(KEYDIR)/hw_key_c.key \ + -p $(KEYDIR)/sw_key_p.key --payload $< --imagefile $<.signed + @printf " ECC $(subst $(obj)/,,$<)\n" + $(ECCTOOL) --inject $<.signed --output $<.signed.ecc --p8 + $(ECCTOOL) --inject $< --output $<.ecc --p8 + @printf " ECC bootblock\n" + dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null + $(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8 + rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad + +files_added:: sign_and_add_ecc endif -- To view, visit https://review.coreboot.org/c/coreboot/+/67065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Gerrit-Change-Number: 67065 Gerrit-PatchSet: 43 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org>

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[XL] Change in coreboot[main]: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80705?usp=email ) Change subject: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II ...................................................................... mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/byte-specification Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/byte_adl.md A src/mainboard/starlabs/byte_adl/Kconfig A src/mainboard/starlabs/byte_adl/Kconfig.name A src/mainboard/starlabs/byte_adl/Makefile.mk A src/mainboard/starlabs/byte_adl/acpi/ec.asl A src/mainboard/starlabs/byte_adl/acpi/mainboard.asl A src/mainboard/starlabs/byte_adl/acpi/sleep.asl A src/mainboard/starlabs/byte_adl/acpi/superio.asl A src/mainboard/starlabs/byte_adl/board_info.txt A src/mainboard/starlabs/byte_adl/bootblock.c A src/mainboard/starlabs/byte_adl/cmos.default A src/mainboard/starlabs/byte_adl/cmos.layout A src/mainboard/starlabs/byte_adl/dsdt.asl A src/mainboard/starlabs/byte_adl/hda_verb.c A src/mainboard/starlabs/byte_adl/include/variants.h A src/mainboard/starlabs/byte_adl/mainboard.c A src/mainboard/starlabs/byte_adl/smbios.c A src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk A src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd A src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt A src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb A src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c A src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c A src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c A src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c A src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd A src/mainboard/starlabs/byte_adl/vboot.c 28 files changed, 1,393 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a0193f0..2f5dd71 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -333,6 +333,8 @@ StarLite Mk V <starlabs/lite_adl.md> StarBook Mk V <starlabs/starbook_tgl.md> StarBook Mk VI <starlabs/starbook_adl.md> +Byte Mk II <starlabs/byte_adl.md> + Flashing devices <starlabs/common/flashing.md> ``` diff --git a/Documentation/mainboard/starlabs/byte_adl.md b/Documentation/mainboard/starlabs/byte_adl.md new file mode 100644 index 0000000..d357a5a --- /dev/null +++ b/Documentation/mainboard/starlabs/byte_adl.md @@ -0,0 +1,83 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel N200 (Alder Lake) +- EC + - ITE IT5570E + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - HDMI video + - DisplayPort video + - USB-C DisplayPort video +- Memory + - 1 x DDR4 SODIMM +- Networking + - 9560 2230 WiFi / Bluetooth + - Realtek RLT8111 1Gbps + - Realtek RLT8125B 2.5Gbps +- Sound + - SoundWire SN6140 + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD +- USB + - 2 x USB 3.1 Gen 2 Type-A (front) + - 1 x USB 3.1 Gen 2 Type-C (front) + - 2 x USB 3.1 Gen 2 Type-A (back) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256.V | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig new file mode 100644 index 0000000..f9b5a17 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/Kconfig @@ -0,0 +1,104 @@ +config BOARD_STARLABS_BYTE_SERIES + def_bool n + select EC_STARLABS_ITE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select VALIDATE_INTEL_DESCRIPTOR + +config BOARD_STARLABS_BYTE_ADL + select BOARD_ROMSIZE_KB_16384 + select BOARD_STARLABS_BYTE_SERIES + select CRB_TPM + select DRIVERS_INTEL_PMC + select EC_STARLABS_MERLIN + select EC_STARLABS_NEED_ITE_BIN + select HAVE_INTEL_PTT + select SOC_INTEL_ALDERLAKE + select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_CRASHLOG + select SPI_FLASH_WINBOND + +if BOARD_STARLABS_BYTE_SERIES + +config CONSOLE_SERIAL + default n if !EDK2_DEBUG + +config D3COLD_SUPPORT + default n + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config EC_GPE_SCI + default 0x6e + +config EC_STARLABS_ADD_ITE_BIN + default n + +config EC_STARLABS_ITE_BIN_PATH + string + depends on EC_STARLABS_NEED_ITE_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" + +config EC_VARIANT_DIR + default "merlin" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin" + +config MAINBOARD_DIR + default "starlabs/byte_adl" + +config MAINBOARD_FAMILY + string + default "Y2" + +config MAINBOARD_PART_NUMBER + default "Byte Mk II" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Byte" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin" + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + default n + +config EDK2_BOOTSPLASH_FILE + string + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select VBOOT_VBNV_FLASH + +config VARIANT_DIR + default "mk_ii" + +endif diff --git a/src/mainboard/starlabs/byte_adl/Kconfig.name b/src/mainboard/starlabs/byte_adl/Kconfig.name new file mode 100644 index 0000000..f46e376 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/Kconfig.name @@ -0,0 +1,4 @@ +comment "Star Labs Byte Series" + +config BOARD_STARLABS_BYTE_ADL + bool "Star Labs Byte Mk II (N200)" diff --git a/src/mainboard/starlabs/byte_adl/Makefile.mk b/src/mainboard/starlabs/byte_adl/Makefile.mk new file mode 100644 index 0000000..84b693e --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/Makefile.mk @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +subdirs-y += variants/$(VARIANT_DIR) + +bootblock-y += bootblock.c + +verstage-$(CONFIG_VBOOT) += vboot.c + +romstage-$(CONFIG_VBOOT) += vboot.c + +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += smbios.c diff --git a/src/mainboard/starlabs/byte_adl/acpi/ec.asl b/src/mainboard/starlabs/byte_adl/acpi/ec.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl b/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl new file mode 100644 index 0000000..34b90af --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" +} diff --git a/src/mainboard/starlabs/byte_adl/acpi/sleep.asl b/src/mainboard/starlabs/byte_adl/acpi/sleep.asl new file mode 100644 index 0000000..7ed74e3 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (MPTS, 1, NotSerialized) +{ + RPTS (Arg0) +} + +Method (MWAK, 1, NotSerialized) +{ + RWAK (Arg0) +} diff --git a/src/mainboard/starlabs/byte_adl/acpi/superio.asl b/src/mainboard/starlabs/byte_adl/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/byte_adl/board_info.txt b/src/mainboard/starlabs/byte_adl/board_info.txt new file mode 100644 index 0000000..86a76f6 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: Byte +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/byte_adl/bootblock.c b/src/mainboard/starlabs/byte_adl/bootblock.c new file mode 100644 index 0000000..ca48bb1 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variants.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/byte_adl/cmos.default b/src/mainboard/starlabs/byte_adl/cmos.default new file mode 100644 index 0000000..ddb2d28 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/cmos.default @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# hardcoded +boot_option=Fallback +# console +debug_level=Debug +# cpu +vtd=Enable +power_profile=Balanced +me_state=Disable +# Devices +wireless=Enable +webcam=Enable +# EC +mirror_flag=Disable diff --git a/src/mainboard/starlabs/byte_adl/cmos.layout b/src/mainboard/starlabs/byte_adl/cmos.layout new file mode 100644 index 0000000..0b4984d --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/cmos.layout @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# Bank: 1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level +# coreboot config options: cpu +#400 8 r 0 reserved for century byte +408 1 e 1 vtd +416 2 e 5 power_profile +424 1 e 4 me_state +432 4 h 0 me_state_counter + +# coreboot config options: Devices +504 1 e 1 wireless + +# coreboot config options: check sums +984 16 h 0 check_sum + +# Bank: 2 +# embedded controller settings (outside the checksummed area) +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 Enable +4 1 Disable + +5 0 Power Saver +5 1 Balanced +5 2 Performance + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/byte_adl/dsdt.asl b/src/mainboard/starlabs/byte_adl/dsdt.asl new file mode 100644 index 0000000..c0936a7 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/dsdt.asl @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20220930 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + + #include <soc/intel/common/block/acpi/acpi/gna.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Star Labs EC */ + #include <ec/starlabs/merlin/acpi/ec.asl> + + Scope (\_SB) + { + /* HID Driver */ + #include <ec/starlabs/merlin/acpi/hid.asl> + + /* Suspend Methods */ + #include <ec/starlabs/merlin/acpi/suspend.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/byte_adl/hda_verb.c b/src/mainboard/starlabs/byte_adl/hda_verb.c new file mode 100644 index 0000000..ca69ef9 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/azalia_device.h> +#include <option.h> +#include <types.h> + +#define AZALIA_CODEC_SN6140 0x14f11f87 + +static const u32 override_verb[] = { + AZALIA_PIN_CFG(0, 0x1a, 0x00000000), +}; + +static void disable_microphone(u8 *base) +{ + azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb)); +} + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (viddid == AZALIA_CODEC_SN6140) { + printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid); + if (get_uint_option("microphone", 1) == 0) + disable_microphone(base); + } +} diff --git a/src/mainboard/starlabs/byte_adl/include/variants.h b/src/mainboard/starlabs/byte_adl/include/variants.h new file mode 100644 index 0000000..0dd41c0 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/include/variants.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include <soc/gpio.h> + +enum cmos_power_profile { + PP_POWER_SAVER = 0, + PP_BALANCED = 1, + PP_PERFORMANCE = 2, +}; +#define NUM_POWER_PROFILES 3 + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback); + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void devtree_update(void); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/byte_adl/mainboard.c b/src/mainboard/starlabs/byte_adl/mainboard.c new file mode 100644 index 0000000..d394f25 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/mainboard.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/ramstage.h> +#include <option.h> +#include <variants.h> + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback) +{ + const unsigned int power_profile = get_uint_option("power_profile", fallback); + return power_profile < NUM_POWER_PROFILES ? power_profile : fallback; +} + +static void init_mainboard(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/byte_adl/smbios.c b/src/mainboard/starlabs/byte_adl/smbios.c new file mode 100644 index 0000000..ab2c211 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/smbios.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <ec/starlabs/merlin/ec.h> +#include <smbios.h> +#include <types.h> +#include <uuid.h> +#include <variants.h> + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = ec_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_sku(void) +{ + return CONFIG_MAINBOARD_FAMILY; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk new file mode 100644 index 0000000..2a505c3 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd b/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd new file mode 100644 index 0000000..3c64b27 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x1000000 { + SI_ALL 0x600000 { + SI_DESC 0x1000 + SI_ME 0x411000 + } + SI_BIOS 0xa00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt new file mode 100644 index 0000000..aa4ea41 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb new file mode 100644 index 0000000..2115042 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -0,0 +1,219 @@ +chip soc/intel/alderlake + # FSP UPDs + register "enable_c6dram" = "true" + register "eist_enable" = "true" + register "cnvi_bt_audio_offload" = "true" + register "cnvi_bt_core" = "true" + register "sagv" = "SaGv_Enabled" + + # Serial I/O + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + # Power + register "pch_slp_s3_min_assertion_width" = "2" # 50ms + register "pch_slp_s4_min_assertion_width" = "3" # 1s + register "pch_slp_sus_min_assertion_width" = "3" # 500ms + register "pch_slp_a_min_assertion_width" = "3" # 2s + + device domain 0 on + device ref igpu on + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref gna on end + device ref xhci on + # Front panel USB Type C + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Back Top USB Type A [5] + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Back Bottom USB Type A [6] + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Front Left USB Type A [3] + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Front Right USB Type A [2] + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Internal Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Back Top USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Back Top USB Type-C"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Back Bottom USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Back Bottom USB Type-C"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Left USB Type-C"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Right USB Type-C"" + register "type" = "UPC_TYPE_USB3_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_dev_slp[0]" = "1" + register "sata_ports_enable[1]" = "1" + register "sata_ports_dev_slp[1]" = "1" + end + device ref pcie_rp9 on # RLT8111 (LAN 1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + + }" + smbios_slot_desc "SlotTypePciExpressGen4x1" + "SlotLengthShort" + "SlotTypePci" + "SlotDataBusWidth4X" + end + device ref pcie_rp10 on # RLT8125B (LAN 2) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypePciExpressGen3X4" + "SlotLengthShort" + "SlotTypePci" + "SlotDataBusWidth4X" + end + device ref pcie_rp12 on # SSD x4 + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypePciExpressGen3X4" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref uart0 on end + device ref pch_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0201" + register "gen3_dec" = "0x000c0081" + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 off end # PS/2 Keyboard + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x14f1 0x035e + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c new file mode 100644 index 0000000..96e0b93 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + struct soc_power_limits_config *soc_conf_4core = + &cfg->power_limits_config[ADL_N_041_6W_CORE]; + + struct device *nic_dev = pcidev_on_root(0x14, 3); + + /* Update PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + disable_turbo(); + soc_conf_4core->tdp_pl1_override = 6; + soc_conf_4core->tdp_pl2_override = 10; + common_config->pch_thermal_trip = 30; + break; + case PP_BALANCED: + soc_conf_4core->tdp_pl1_override = 10; + soc_conf_4core->tdp_pl2_override = 25; + common_config->pch_thermal_trip = 25; + break; + case PP_PERFORMANCE: + soc_conf_4core->tdp_pl1_override = 20; + soc_conf_4core->tdp_pl2_override = 35; + common_config->pch_thermal_trip = 20; + break; + } + + /* Enable/Disable Bluetooth based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) { + cfg->usb2_ports[9].enable = 0; + nic_dev->enabled = 0; + } +} diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c new file mode 100644 index 0000000..6387146 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* H10: UART0 RXD Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11: UART0 TXD Debug Connector */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* GPD0: Battery Low */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: Charger Connected */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN Wake */ + PAD_NC(GPD2, NONE), + /* GPD3: Power Button */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: Sleep S3 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: Sleep S4 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: Sleep A */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: Power Adapter Disable */ + PAD_CFG_GPO(GPD7, 0, PWROK), + /* GPD8: Suspend Clock */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: Wireless LAN Sleep */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: Sleep S5 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LAN PHY Enable */ + PAD_NC(GPD11, NONE), + + /* A0: ESPI IO 0 */ + /* A1: ESPI IO 1 */ + /* A2: ESPI IO 2 */ + /* A3: ESPI IO 3 */ + /* A4: ESPI CS 0 */ + /* A5: Not Connected */ + PAD_NC(GPP_A5, NONE), + /* A6: Not Connected */ + PAD_NC(GPP_A6, NONE), + /* A7: Embedded Controller SCI */ + PAD_NC(GPP_A7, NONE), + /* A8: Not Connected */ + PAD_NC(GPP_A8, NONE), + /* A9: ESPI Clock */ + /* A10: ESPI Reset */ + /* A11: Not Connected */ + PAD_NC(GPP_A11, NONE), + /* A12: PCH M.2 SSD PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13: BlueTooth RF Kill */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14: Type C VBUS OverCurrent */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15: Test Point 3 */ + PAD_NC(GPP_A15, NONE), + /* A16: USB 2 OverCurrent B */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17: Not Connected */ + PAD_NC(GPP_A17, NONE), + /* A18: DDI B DP HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19: TCP0 HPD */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), + /* A20: Test Point 2 */ + PAD_NC(GPP_A20, NONE), + /* A21: Fingerprint Reader Interrupt */ + PAD_NC(GPP_A21, NONE), + /* A22: Fingerprint Reader Reset */ + PAD_NC(GPP_A22, NONE), + /* A23: Not Connected */ + PAD_NC(GPP_A23, NONE), + + + /* B0: Core Vendor ID 0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1: Core Vendor ID 1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2: BC PROCHOT */ + PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* B3: Not Connected */ + PAD_NC(GPP_B3, NONE), + /* B4: Not Connected */ + PAD_NC(GPP_B4, NONE), + /* B5: I2C 2 SDA Touch Panel SDA */ + PAD_NC(GPP_B5, NONE), + /* B6: I2C 2 SCL Touch Panel Clock */ + PAD_NC(GPP_B6, NONE), + /* B7: I2C 3 SDA Touchpad SDA */ + PAD_NC(GPP_B7, NONE), + /* B8: I2C 3 SCL Touchpad Clock */ + PAD_NC(GPP_B8, NONE), + /* B9: Not Connected */ + PAD_NC(GPP_B9, NONE), + /* B10: Not Connected */ + PAD_NC(GPP_B10, NONE), + /* B11: I2C PMC PD Interrupt Test Point 28 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12: PM SLP S0 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13: PLT RST */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: Top Swap Override Weak Internal PD 20K + High: Enabled + Low: Disabled */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* B15: Not Connected */ + PAD_NC(GPP_B15, NONE), + /* B16: Not Connected */ + PAD_NC(GPP_B16, NONE), + /* B17: Not Connected */ + PAD_NC(GPP_B17, NONE), + /* B18: Reboot Support Weak Internal PD 20K + High: Disabled + Low: Enabled */ + PAD_NC(GPP_B18, NONE), + /* B19: Not Connected */ + PAD_NC(GPP_B19, NONE), + /* B20: Not Connected */ + PAD_NC(GPP_B20, NONE), + /* B21: Not Connected */ + PAD_NC(GPP_B21, NONE), + /* B22: Not Connected */ + PAD_NC(GPP_B22, NONE), + /* B23: Not used MiPi Camera */ + PAD_NC(GPP_B23, NONE), + /* B24: Not Connected */ + PAD_NC(GPP_B24, NONE), + /* B25: Not Connected */ + PAD_NC(GPP_B25, NONE), + + /* C0: SMB Clock */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1: SMB Data */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2: TLS Confidentiality Weak Internal PD 20K + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* C3: SML 0 Clock */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4: SML 0 Data */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5: Boot Strap Weak Internal PD 20K + Low: ESPI + High: Disabled */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* C6: SML 1 Clock */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7: SML 1 Data */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8: Not Connected */ + PAD_NC(GPP_C8, NONE), + /* C9: Not Connected */ + PAD_NC(GPP_C9, NONE), + /* C10: Not Connected */ + PAD_NC(GPP_C10, NONE), + /* C11: Not Connected */ + PAD_NC(GPP_C11, NONE), + /* C12: Not Connected */ + PAD_NC(GPP_C12, NONE), + /* C13: Not Connected */ + PAD_NC(GPP_C13, NONE), + /* C14: Not Connected */ + PAD_NC(GPP_C14, NONE), + /* C15: Not Connected */ + PAD_NC(GPP_C15, NONE), + /* C16: Not Connected */ + PAD_NC(GPP_C16, NONE), + /* C17: Not Connected */ + PAD_NC(GPP_C17, NONE), + /* C18: Not Connected */ + PAD_NC(GPP_C18, NONE), + /* C19: Not Connected */ + PAD_NC(GPP_C19, NONE), + /* C20: Not Connected */ + PAD_NC(GPP_C20, NONE), + /* C21: Not Connected */ + PAD_NC(GPP_C21, NONE), + /* C22: Not Connected */ + PAD_NC(GPP_C22, NONE), + /* C23: Not Connected */ + PAD_NC(GPP_C23, NONE), + + /* D0: Not used Audio ID 0 */ + PAD_NC(GPP_D0, NONE), + /* D1: Not used Audio ID 1 */ + PAD_NC(GPP_D1, NONE), + /* D2: Not used Audio ID 2 */ + PAD_NC(GPP_D2, NONE), + /* D3: Not Connected */ + PAD_NC(GPP_D3, NONE), + /* D4: Not Connected */ + PAD_NC(GPP_D4, NONE), + /* D5: Clock Request 0 PCH M.2 SSD */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6: Clock Request 1 Wireless LAN */ + PAD_NC(GPP_D6, NONE), + /* D7: Clock Request 2 LAN 1 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8: Clock Request 3 LAN 2 */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9: GSPI 2 FPS */ + PAD_NC(GPP_D9, NONE), + /* D10: GSPI 2 Clock */ + PAD_NC(GPP_D10, NONE), + /* D11: GSPI 2 MISO FPS */ + PAD_NC(GPP_D11, NONE), + /* D12: GSPI 2 MOSI FPS */ + PAD_NC(GPP_D12, NONE), + /* D13: Wireless LAN Wake */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14: Test Point 10 */ + PAD_NC(GPP_D14, NONE), + /* D15: Not Connected */ + PAD_NC(GPP_D15, NONE), + /* D16: PCH M.2 SSD Power Enable */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* D17: Not Connected */ + PAD_NC(GPP_D17, NONE), + /* D18: Not Connected */ + PAD_NC(GPP_D18, NONE), + /* D19: Test Point 6 */ + PAD_NC(GPP_D19, NONE), + + /* E0: SATA x PCIe */ + PAD_NC(GPP_E0, NONE), + /* E1: Not used Accelerometer Interrupt */ + PAD_NC(GPP_E1, NONE), + /* E2: Not Connected */ + PAD_NC(GPP_E2, NONE), + /* E3: WiFi RF Kill */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4: Test Point 7 */ + PAD_NC(GPP_E4, NONE), + /* E5: Not Connected */ + PAD_NC(GPP_E5, NONE), + /* E6: JTAG ODT No internal PD + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + /* E7: Embedded Controller SMI */ + PAD_NC(GPP_E7, NONE), + /* E8: DRAM Sleep */ + PAD_NC(GPP_E8, NONE), + /* E9: USB OverCurrent 0 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10: Not Connected */ + PAD_NC(GPP_E10, NONE), + /* E11: Not Connected */ + PAD_NC(GPP_E11, NONE), + /* E12: Touchpad Interrupt */ + PAD_NC(GPP_E12, NONE), + /* E13: PWD Amplifier Input */ + PAD_CFG_GPO(GPP_E13, 0, PLTRST), + /* E14: EDP HPD */ + PAD_NC(GPP_E14, NONE), + /* E15: Not Connected LAN RESET */ + PAD_NC(GPP_E15, NONE), + /* E16: Not Connected */ + PAD_NC(GPP_E16, NONE), + /* E17: Test Point 1 */ + PAD_NC(GPP_E17, NONE), + /* E18: Not Connected */ + PAD_NC(GPP_E18, NONE), + /* E19: Thunderbolt LSX RXD */ + PAD_NC(GPP_E19, NONE), + /* E20: Not Connected */ + PAD_NC(GPP_E20, NONE), + /* E21: Not Connected */ + PAD_NC(GPP_E21, NONE), + /* E22: Not Connected */ + PAD_NC(GPP_E22, NONE), + /* E23: Not Connected */ + PAD_NC(GPP_E23, NONE), + + /* F0: CNV BRI Data */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1: CNV BRI Response */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2: CNV RGI Data */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3: CNV RGI Response */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4: CNV RF Reset */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5: Not used MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F6: CNV PA Blanking */ + PAD_NC(GPP_F6, NONE), + /* F7: TBT LSX VCCIO Weak Internal PD 20K + Low: 1.8V + High: 3.3V */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + /* F8: Not Connected */ + PAD_NC(GPP_F8, NONE), + /* F9: */ + PAD_NC(GPP_F9, NONE), + /* F10: Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* F11: Not Connected */ + PAD_NC(GPP_F11, NONE), + /* F12: Not Connected */ + PAD_NC(GPP_F12, NONE), + /* F13: Not Connected */ + PAD_NC(GPP_F13, NONE), + /* F14: Not Connected */ + PAD_NC(GPP_F14, NONE), + /* F15: Not Connected */ + PAD_NC(GPP_F15, NONE), + /* F16: Not Connected */ + PAD_NC(GPP_F16, NONE), + /* F17: Not used Touch Panel Reset */ + PAD_NC(GPP_F17, NONE), + /* F18: Not used Touch Panel Interrupt */ + PAD_NC(GPP_F18, NONE), + /* F19: Not Connected */ + PAD_NC(GPP_F19, NONE), + /* F20: CPU M.2 SSD Reset */ + PAD_NC(GPP_F20, NONE), + /* F21: GPPC_F21 */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22: Not Connected */ + PAD_NC(GPP_F22, NONE), + /* F23: Not Connected */ + PAD_NC(GPP_F23, NONE), + + /* H0: PCH M.2 SSD Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* H2: Wireless LAN Reset */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* H3: Not Connected */ + PAD_NC(GPP_H3, NONE), + /* H4: I2C 0 SDA GSensor */ + PAD_NC(GPP_H4, NONE), + /* H5: I2C 0 SDL GSensor */ + PAD_NC(GPP_H5, NONE), + /* H6: Test Point 4 */ + PAD_NC(GPP_H6, NONE), + /* H7: Test Point 5 */ + PAD_NC(GPP_H7, NONE), + /* H8: Not Connected */ + PAD_NC(GPP_H8, NONE), + /* H9: Not Connected */ + PAD_NC(GPP_H9, NONE), + /* H12: Not Connected */ + PAD_NC(GPP_H12, NONE), + /* H13: PCH M.2 SSD Device Sleep */ + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* H14: Not Connected */ + PAD_NC(GPP_H14, NONE), + /* H15: DDPB Control Clock */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16: Not Connected */ + PAD_NC(GPP_H16, NONE), + /* H17: DDPB Control Data */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: CPI C10 Gate */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19: Clock Request 4 */ + PAD_NC(GPP_H19, NONE), + /* H20: Not Connected */ + PAD_NC(GPP_H20, NONE), + /* H21: Not Connected */ + PAD_NC(GPP_H21, NONE), + /* H22: Not Connected */ + PAD_NC(GPP_H22, NONE), + /* H23: Clock Request 5 */ + PAD_NC(GPP_H23, NONE), + + /* S0: Not Connected */ + PAD_NC(GPP_S0, NONE), + /* S1: Not Connected */ + PAD_NC(GPP_S1, NONE), + /* S2: Not Connected */ + PAD_NC(GPP_S2, NONE), + /* S3: Not Connected */ + PAD_NC(GPP_S3, NONE), + /* S4: Not Connected */ + PAD_NC(GPP_S4, NONE), + /* S5: Not Connected */ + PAD_NC(GPP_S5, NONE), + /* S6: DMIC Clock */ + PAD_NC(GPP_S6, NONE), + /* S7: DMIC Data */ + PAD_NC(GPP_S7, NONE), + + /* T0: Not Connected */ + PAD_NC(GPP_T0, NONE), + /* T1: Not Connected */ + PAD_NC(GPP_T1, NONE), + /* T2: Not Connected */ + PAD_NC(GPP_T2, NONE), + /* T3: Not Connected */ + PAD_NC(GPP_T3, NONE), + /* T4: Not Connected */ + PAD_NC(GPP_T4, NONE), + /* T5: Not Connected */ + PAD_NC(GPP_T5, NONE), + /* T6: Not Connected */ + PAD_NC(GPP_T6, NONE), + /* T7: Not Connected */ + PAD_NC(GPP_T7, NONE), + /* T8: Not Connected */ + PAD_NC(GPP_T8, NONE), + /* T9: Not Connected */ + PAD_NC(GPP_T9, NONE), + /* T10: Not Connected */ + PAD_NC(GPP_T10, NONE), + /* T11: Not Connected */ + PAD_NC(GPP_T11, NONE), + /* T12: Not Connected */ + PAD_NC(GPP_T12, NONE), + /* T13: Not Connected */ + PAD_NC(GPP_T13, NONE), + /* T14: Not Connected */ + PAD_NC(GPP_T14, NONE), + /* T15: Not Connected */ + PAD_NC(GPP_T15, NONE), + + /* R0: HDA BCLK */ + PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), + /* R1: HDA SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* R2: HDA SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* R3: HDA SDI */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* R4: HDA Reset */ + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), + /* R5: Not Connected */ + PAD_NC(GPP_R5, NONE), + /* R6: Not Connected */ + PAD_NC(GPP_R6, NONE), + /* R7: Not Connected */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c new file mode 100644 index 0000000..46c8738 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <stdint.h> + +const uint32_t cim_verb_data[] = { + /* coreboot specific header */ + 0x14f11f87, /* Codec Vendor / Device ID: SoundWire SN6140 */ + 0x14f1035e, /* Subsystem ID */ + 17, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table */ + AZALIA_SUBVENDOR(0, 0x14f1035e), + + /* + * Configuration: + * + * Port A (0x16) 04214040 Headphone + * Port B (0x18) 40F001F0 + * Port C (0x1a) 90A72150 DMIC + * Port D (0x19) 04A19020 Headset Microphone + * Port E (0x1d) 0 + * Port F (0x1e) 0 + * Port G (0x17) 90173160 Speaker + * Port H (0x1f) 0 + * Port I (0x21) 40f001f0 + * Port M (0x22) 0 + */ + + 0x01c49100, + 0x000f0000, + 0x000f0000, + 0x000f0000, + + 0x000f0000, + 0x01c49000, + 0x000f0000, + 0x000f0000, + + 0x0017ff00, + 0x0017ff00, + 0x000f0000, + 0x000f0000, + + 0x000f0000, + 0x000f0000, + 0x000f0000, + 0x000f0000, + + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + + 0x0017205e, /* SSID */ + 0x00172103, + 0x001722f1, + 0x00172314, + + AZALIA_PIN_CFG(0, 0x16, 0x04214040), + AZALIA_PIN_CFG(0, 0x18, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1a, 0x90a72150), + AZALIA_PIN_CFG(0, 0x19, 0x04a19020), + AZALIA_PIN_CFG(0, 0x1d, 0x00000000), + AZALIA_PIN_CFG(0, 0x1e, 0x00000000), + AZALIA_PIN_CFG(0, 0x17, 0x90173160), + AZALIA_PIN_CFG(0, 0x1f, 0x00000000), + AZALIA_PIN_CFG(0, 0x21, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x00000000), + + 0x01c31028, /* Class D Gain */ + 0x01b30420, /* Set EAPD */ + 0x01c31028, + 0x01b30420, + + 0x80862815, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18561010), + AZALIA_PIN_CFG(2, 0x0a, 0x18561010), + AZALIA_PIN_CFG(2, 0x0b, 0x18561010), + AZALIA_PIN_CFG(2, 0x0c, 0x18561010), + AZALIA_PIN_CFG(2, 0x0d, 0x18561010), + AZALIA_PIN_CFG(2, 0x0e, 0x18561010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c new file mode 100644 index 0000000..502411b --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <types.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + }; + + const bool half_populated = true; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + } + }, + }; + + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; +}; diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd b/src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd new file mode 100644 index 0000000..66b62cb --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd @@ -0,0 +1,24 @@ +FLASH 0x1000000 { + SI_ALL 0x600000 { + SI_DESC 0x1000 + SI_ME 0x411000 + } + SI_BIOS 0xa00000 { + EC@0x0 0x20000 + RO_SECTION@0x20000 0x253000 { + FMAP@0x0 0x1000 + COREBOOT(CBFS)@0x1000 0x210000 + GBB@0x211000 0x40000 + RO_FRID@0x251000 0x40 + RO_VPD(PRESERVE)@0x252000 0x1000 + } + MISC_RW@0x273000 0x10000 { + RW_MRC_CACHE@0x0 0x10000 + } + SMMSTORE@0x290000 0x40000 + CONSOLE@0x2d0000 0x20000 + RW_NVRAM(PRESERVE)@0x2f0000 0x6000 + RW_VPD(PRESERVE)@0x2f6000 0x2000 + RW_LEGACY(CBFS)@0x32e000 0x60000 + } +} diff --git a/src/mainboard/starlabs/byte_adl/vboot.c b/src/mainboard/starlabs/byte_adl/vboot.c new file mode 100644 index 0000000..8511825 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/vboot.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> + +int get_recovery_mode_switch(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Gerrit-Change-Number: 80705 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: include/assert.h: Deal with GCC LTO false positives
by Arthur Heymans (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: include/assert.h: Deal with GCC LTO false positives ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84208/comment/ea333bf1_20f59a46?us… : PS2, Line 7: FIXME > Got it. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 13:41:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO
by Arthur Heymans (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84033?usp=email to look at the new patch set (#35). Change subject: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO ...................................................................... [NOT_FOR_MERGE]Kconfig: Build all targets with LTO ARM, RISCV and PPC64 with GCC LTO fails hard. Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84033/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/84033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Gerrit-Change-Number: 84033 Gerrit-PatchSet: 35 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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