coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 70: (1 comment) File src/soc/intel/pantherlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/dab5768f_af8d4fde?us… : PS49, Line 260: GPP_E_OFFSET > Subrata, I just contacted our EDS owner and was told that GPP_E0 is a no connect pin (not bonded out to the package) in PTL. In addition, he points out to reference PTL GPIO Implementation doc for details (#817954). Can you try if you can see this document? if you are saying GPP_E0 doesn't even exist for PTL then first PIN should be `(PAD_CFG_DW0_xxgpp_e_1)` and start offset should be 0x9b0 -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 70 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Sep 2024 17:03:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 70: (1 comment) File src/soc/intel/pantherlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/702175cc_658b1b04?us… : PS49, Line 260: GPP_E_OFFSET > > Subrata, […] Subrata, I just contacted our EDS owner and was told that GPP_E0 is a no connect pin (not bonded out to the package) in PTL. In addition, he points out to reference PTL GPIO Implementation doc for details (#817954). Can you try if you can see this document? -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 70 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Sep 2024 16:20:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 CMT port
by Riku Viitanen (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Felix Singer, Nicholas Chin, Nico Huber, Paul Menzel. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/79745?usp=email ) Change subject: mb/hp: Add Compaq Elite 8300 CMT port ...................................................................... Patch Set 18: (14 comments) Patchset: PS18: will convert to variant next File src/mainboard/hp/compaq_elite_8300_cmt/Kconfig: https://review.coreboot.org/c/coreboot/+/79745/comment/80c69211_36a9f33a?us… : PS17, Line 1: if > ```suggestion […] Done File src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name: https://review.coreboot.org/c/coreboot/+/79745/comment/9e6dab2c_7bc5f19f?us… : PS17, Line 1: co > ```suggestion […] Done File src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/79745/comment/a6956532_74b38021?us… : PS17, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */ > ```suggestion […] Done File src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79745/comment/582c6075_18e61260?us… : PS17, Line 4: register "gfx.use_spread_spectrum_clock" = "0" : register "gpu_dp_b_hotplug" = "0" : register "gpu_dp_c_hotplug" = "0" : r > Remove, since initialized with 0. Done https://review.coreboot.org/c/coreboot/+/79745/comment/390c2249_54b1fce9?us… : PS17, Line 13: device ref host_bridge on end # Host bridge Host bridge : device ref peg10 on end # PEG : device ref igd on end # iGPU > Please remove superfluous comments duplicating the device names. More are below. […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/0b61e11e_84281b76?us… : PS17, Line 18: register "docking_supported" = "0" : > Remove, initialized with 0. […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/f953431f_9fa5b642?us… : PS17, Line 21: register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" : > Remove, initialized with 0. […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/2cf7352a_a88d617d?us… : PS17, Line 49: device ref mei2 off end : device ref me_ide_r off end : device ref me_kt off end : > Remove, disabled by default. […] Done File src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl: https://review.coreboot.org/c/coreboot/+/79745/comment/094741a8_2b0ac028?us… : PS17, Line 11: 0x20141018 /* OEM revision */ > ```suggestion […] Done File src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c: https://review.coreboot.org/c/coreboot/+/79745/comment/8eced96e_edf6a38a?us… : PS17, Line 10: AZALIA_PIN_CFG(0, 0x12, 0x411111f0), > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/0bf70770_68ad9d67?us… : PS17, Line 13: AZALIA_PIN_CFG(0, 0x18, 0x411111f0), : A > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/321a7514_d8dde9ba?us… : PS17, Line 18: AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/79745/comment/f6a8a7c6_8fe8c469?us… : PS17, Line 27: AZALIA_PIN_CFG(3, 0x07, 0x58560030), : : }; > Remove blank line […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 18 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 16:09:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 CMT port
by Riku Viitanen (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Felix Singer, Nicholas Chin, Nico Huber, Paul Menzel, Riku Viitanen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79745?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/hp: Add Compaq Elite 8300 CMT port ...................................................................... mb/hp: Add Compaq Elite 8300 CMT port Based on autoport and Z220 SuperIO code. With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780 (must use proprietary driver instead). Tested by xilynx / spot_ on #libreboot: - i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1 - Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1 - Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS - All SATA ports - Audio: internal speaker, headphone and microphone plugs - Rebooting - S3 suspend and wake - libgfxinit: VGA, DisplayPort - Ethernet - Super I/O: fan speeds stay in control - GPU in PEG slot Untested: - EHCI debugging - Other PCI/PCIe slots - PS/2 - Serial, parallel ports Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/hp/compaq_elite_8300_cmt/Kconfig A src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name A src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk A src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl A src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c A src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt A src/mainboard/hp/compaq_elite_8300_cmt/cmos.default A src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout A src/mainboard/hp/compaq_elite_8300_cmt/data.vbt A src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb A src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl A src/mainboard/hp/compaq_elite_8300_cmt/early_init.c A src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads A src/mainboard/hp/compaq_elite_8300_cmt/gpio.c A src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c A src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c 18 files changed, 655 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/79745/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 18 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/kahlee: Add Kconfig to set IGD UMA allocation
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84235?usp=email ) Change subject: mb/google/kahlee: Add Kconfig to set IGD UMA allocation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Gerrit-Change-Number: 84235 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 16:00:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/kahlee: Add Kconfig to set IGD UMA allocation
by Matt DeVillier (Code Review) 06 Sep '24

06 Sep '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84235?usp=email ) Change subject: mb/google/kahlee: Add Kconfig to set IGD UMA allocation ...................................................................... mb/google/kahlee: Add Kconfig to set IGD UMA allocation Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/baseboard/devicetree.cb 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84235/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 86632db..880209e 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -172,4 +172,31 @@ default n if CHROMEOS default y +choice + prompt "UMA Memory Allocation" + default UMA_SIZE_32MB + help + The amount of system memory allocated for the integrated GPU + +config UMA_SIZE_32MB + bool "32MB" + +config UMA_SIZE_64MB + bool "64MB" + +config UMA_SIZE_128MB + bool "128MB" + +config UMA_SIZE_256MB + bool "256MB" + +endchoice + +config UMA_SIZE_IN_MB + int + default 32 if UMA_SIZE_32MB + default 64 if UMA_SIZE_64MB + default 128 if UMA_SIZE_128MB + default 256 if UMA_SIZE_256MB + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index ef7839d..ca8933a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -8,7 +8,7 @@ }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "CONFIG_UMA_SIZE_IN_MB * MiB" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" -- To view, visit https://review.coreboot.org/c/coreboot/+/84235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Gerrit-Change-Number: 84235 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 70: (2 comments) File src/soc/intel/pantherlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/83789/comment/6f30beae_f3100478?us… : PS49, Line 436: Name (JTAG, Package (0x02) > Add a TODO task in cros bug: PTL SOC Code Cleanup […] Acknowledged File src/soc/intel/pantherlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/86e83aed_571f895c?us… : PS49, Line 260: GPP_E_OFFSET > Subrata, > > I've asked to fix this a while back. and it got fixed in July. Can you check newer release of EDS? i still don't see GPP_E0. Can you please create yet another TODO and mark this comment resolved ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 70 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Sep 2024 15:56:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Marshall Dawson (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Marshall Dawson has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/f5b98def_8b6beed8?us… : PS3, Line 22: /disable > Done Sorry but I believe the commit message should read "passed to amdfwtool to enable...". -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 15:45:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Subrata Banik (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Sowmya Aralguppe, Wonkyu Kim. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/a62e1973_8dc3a9cb?us… : PS13, Line 23: The issue addressed by this commit can be observed with the following : experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to : 0x400000 (4 MB). > > This isn't a real issue, it's just a hypothesis that CONFIG\_DCACHE\_RAM\_SIZE is larger than the way size. > > The coreboot enhanced NEM code allows `CONFIG_DCACHE_RAM_SIZE` requiring multiple ways but it violate the Alder Lake, Meteor Lake and Panther Lake specification if such a configuration is used ⇒ the code is wrong and this is the issue these CL are addressing. These CL address a coreboot Intel eNEM code issue not a Google board issue. > > If you believe that `CONFIG_DCACHE_RAM_SIZE` should never be larger than the effective way size, then why does the bootblock eNEM support multiple ways ? And why is violating the specification by not considering the effective way size ? > > If you refuse the code to be fixed arguing that no configuration is taking advantage of it, please implement a mechanism in bootblock limiting the configuration to one **effective** way and remove the support for multiple ways. My only objective here is to fix code that does not comply with the specification and I was able to verify the code does not work by tweaking the configuration. *I tweaked the configuration, not the code*. > > My experiments demonstrated that 4MB works like a charm only with these two CLs. I will get back to you by next week early. -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 Sep 2024 15:12:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Bao Zheng (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/4f7ac30d_f78c7cf7?us… : PS3, Line 22: /disable > nit: based on the code change, it appears that 'no recovery' is the default, and the flag is passed […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 15:11:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>

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coreboot-gerrit September 2024