coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
3342 discussions

[S] Change in coreboot[main]: payloads/depthcharge: Add default 64-bit libpayload config
by Wonkyu Kim (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Jérémy Compostella, Martin L Roth, Paul Menzel, Subrata Banik. Wonkyu Kim has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84107?usp=email ) Change subject: payloads/depthcharge: Add default 64-bit libpayload config ...................................................................... Patch Set 8: (1 comment) File payloads/libpayload/configs/defconfig_64: https://review.coreboot.org/c/coreboot/+/84107/comment/1209f834_715b1e89?us… : PS8, Line 1: # NOTE: remove to test _LP64 issue: CONFIG_LP_ARCH_X86_64=y > If CONFIG_LP_ARCH_X86_64=y is included, we will run into the issue shown in https://qa.coreboot. […] If this is commented out it's same as defconfig. Can it be related to below make file? payloads/libpayload/curses/Makefile.mk:41:INCLUDES += -D_LP64=0 -Icurses/$(PDCURSES) -Icurses/pdcurses-backend -Icurses/menu -Icurses/form -- To view, visit https://review.coreboot.org/c/coreboot/+/84107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060 Gerrit-Change-Number: 84107 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Sep 2024 00:51:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB
by Matt DeVillier (Code Review) 06 Sep '24

06 Sep '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84237?usp=email ) Change subject: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB ...................................................................... mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the selected value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS which is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/zork/Kconfig D src/mainboard/google/zork/data.apcb M src/mainboard/google/zork/spd/Makefile.mk A src/mainboard/google/zork/uma_128.apcb A src/mainboard/google/zork/uma_256.apcb A src/mainboard/google/zork/uma_512.apcb A src/mainboard/google/zork/uma_64.apcb 7 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84237/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 1fcd06b..1b38d27 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -301,4 +301,25 @@ select SAR_ENABLE select USE_SAR +choice + prompt "UMA Memory Allocation" + default ZORK_UMA_SIZE_64MB if CHROMEOS + default ZORK_UMA_SIZE_128MB + help + The amount of system memory allocated for the integrated GPU. + +config ZORK_UMA_SIZE_64MB + bool "64MB" + +config ZORK_UMA_SIZE_128MB + bool "128MB" + +config ZORK_UMA_SIZE_256MB + bool "256MB" + +config ZORK_UMA_SIZE_512MB + bool "512MB" + +endchoice + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/spd/Makefile.mk b/src/mainboard/google/zork/spd/Makefile.mk index 3e6509d..1f0b20c 100644 --- a/src/mainboard/google/zork/spd/Makefile.mk +++ b/src/mainboard/google/zork/spd/Makefile.mk @@ -5,7 +5,16 @@ APCB_SOURCES=$(foreach f, $(basename $(notdir $(SPD_SOURCES))), $(obj)/APCB_$(f).gen) # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_NAME=data.apcb +ifeq ($(CONFIG_ZORK_UMA_SIZE_64MB),y) +APCB_NAME=uma_64.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_128MB),y) +APCB_NAME=uma_128.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_256MB),y) +APCB_NAME=uma_256.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_512MB),y) +APCB_NAME=uma_512.apcb +endif + APCB_PATH=$(src)/mainboard/$(MAINBOARDDIR) $(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)%.hex \ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_128.apcb similarity index 97% rename from src/mainboard/google/zork/data.apcb rename to src/mainboard/google/zork/uma_128.apcb index ee12694..fd605b4 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_128.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_256.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_256.apcb index ee12694..f3bd14f 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_256.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_512.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_512.apcb index ee12694..0914c2a 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_512.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_64.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_64.apcb index ee12694..99abf34 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_64.apcb Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/84237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Gerrit-Change-Number: 84237 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XL] Change in coreboot[main]: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
by Maxim (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83107?usp=email to look at the new patch set (#21). Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard ...................................................................... mb/asrock: Add Asrock Industrial IMB-1222 motherboard ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX motherboard [1]. Working: - Dual Channel DDR4 2933/2666/2400 MHz; - Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver); - DP (both), HDMI; - PCIe x16 Slot (Gen3); - SATA ports; - USB 2.0 ports; - USB 3.0 ports; - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi); - M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1); - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3); - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps; - LAN2 Intel I219LM, 10/100/1000 Mbps; - Realtek ALC887 HD Audio (line-out, mic-in); - COM 1/2/3/4 ports; - onboard speaker; - HWM/FANs control (fintek f81966); - S3 suspend and wake; - TPM; - disabling ME (me_cleaner); - boots Ubuntu 22.04/24.04 (SeaBIOS, Linuxboot, edk2 [2]). Unknown/untested: - USB3.0 in M.2 Key-B 3042/3052 slot; - eDP/LVDS; - PCIe riser cards; - SPDIF. Known issues: - there is no video output in firmware with edk2 [2]. There is no schematic/boardview, reverse engineering only. This port is based on system76/bonw14 because it has a similar topology. [1] https://web.archive.org/web/20220924171403/https:// www.asrockind.com/en-gb/IMB-1222 [2] MrChromebox' edk2 fork, https://github.com/mrchromebox/edk2 uefipayload_202309 branch Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A Documentation/mainboard/asrock/imb-1222.md M Documentation/mainboard/index.md A src/mainboard/asrock/imb-1222/Kconfig A src/mainboard/asrock/imb-1222/Kconfig.name A src/mainboard/asrock/imb-1222/Makefile.mk A src/mainboard/asrock/imb-1222/acpi/mainboard.asl A src/mainboard/asrock/imb-1222/acpi/sleep.asl A src/mainboard/asrock/imb-1222/board_info.txt A src/mainboard/asrock/imb-1222/bootblock.c A src/mainboard/asrock/imb-1222/cmos.default A src/mainboard/asrock/imb-1222/cmos.layout A src/mainboard/asrock/imb-1222/data.vbt A src/mainboard/asrock/imb-1222/devicetree.cb A src/mainboard/asrock/imb-1222/dsdt.asl A src/mainboard/asrock/imb-1222/gma-mainboard.ads A src/mainboard/asrock/imb-1222/gpio.c A src/mainboard/asrock/imb-1222/gpio_beep.c A src/mainboard/asrock/imb-1222/hda_verb.c A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h A src/mainboard/asrock/imb-1222/include/mainboard/superio.h A src/mainboard/asrock/imb-1222/panic.c A src/mainboard/asrock/imb-1222/ramstage.c A src/mainboard/asrock/imb-1222/romstage.c A src/mainboard/asrock/imb-1222/superio.c 24 files changed, 1,310 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/83107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Gerrit-Change-Number: 83107 Gerrit-PatchSet: 21 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Jérémy Compostella (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/40911c81_0d1ee73d?us… : PS13, Line 23: The issue addressed by this commit can be observed with the following : experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to : 0x400000 (4 MB). > But my question is where is the doc to refer to understand the formula to calculate the eff_way_size (Therefore, we instead compute the effective way size as the biggest of power of two of the way size which works across all three platforms.) I don't see any document that explains the logic mentioned by you in the commit section? that we should only keep the most significant bit position and mask rest to determine the effective way size. On Alder Lake, the External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides a way to compute the effective cache size (and effective way size) by reading the number of CBO using MSR 0x396. I would not qualify this section of the documentation to be crystal clear but the idea is there. Since Meteor Lake does not have this MSR, the recommendation is to compute the effective cache size following CNDA 1433518 page 15 and determine the NEM size based on the power of 2 of bank number. This CL is implementing the same principle (also aligned with MTL HAS): 1- consider the effective way size for NEM size computation instead of the way size. 2- Compute the effective way size as the biggest power of two of the way size. -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 Sep 2024 22:37:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Alexander Couzens, Krystian Hebel, Michał Żygowski, Nico Huber, Piotr Król. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/79612?usp=email ) Change subject: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > i think i just used what's in the blob repo and iirc that also matched what i pulled form a pre-buil […] ouch, turns out that the board i tested this on is a version without the 9th dram chip needed for ecc. so this might just work on a board that has the 9th dram chip -- To view, visit https://review.coreboot.org/c/coreboot/+/79612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb0cb117bedf900642e93c556a64800e1e52b6ea Gerrit-Change-Number: 79612 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 22:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
by Maxim (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83107?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard ...................................................................... mb/asrock: Add Asrock Industrial IMB-1222 motherboard ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX motherboard [1]. Working: - Dual Channel DDR4 2933/2666/2400 MHz; - Intel UHD Graphics (VGA Option ROM, libgfxinit); - DP (both), HDMI; - PCIe x16 Slot (Gen3); - SATA ports; - USB 2.0 ports; - USB 3.0 ports; - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi); - M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1); - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3); - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps; - LAN2 Intel I219LM, 10/100/1000 Mbps; - Realtek ALC887 HD Audio (line-out, mic-in); - COM 1/2/3/4 ports; - onboard speaker; - HWM/FANs control (fintek f81966); - S3 suspend and wake; - TPM; - disabling ME (me_cleaner); - boots Ubuntu 22.04/24.04 (SeaBIOS, Linuxboot, edk2 [2]). Unknown/untested: - USB3.0 in M.2 Key-B 3042/3052 slot; - eDP/LVDS; - PCIe riser cards; - SPDIF. Known issues: - there is no video output in firmware with edk2 [2]. There is no schematic/boardview, reverse engineering only. This port is based on system76/bonw14 because it has a similar topology. [1] https://web.archive.org/web/20220924171403/https:// www.asrockind.com/en-gb/IMB-1222 [2] MrChromebox' edk2 fork, https://github.com/mrchromebox/edk2 uefipayload_202309 branch Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A Documentation/mainboard/asrock/imb-1222.md M Documentation/mainboard/index.md A src/mainboard/asrock/imb-1222/Kconfig A src/mainboard/asrock/imb-1222/Kconfig.name A src/mainboard/asrock/imb-1222/Makefile.mk A src/mainboard/asrock/imb-1222/acpi/mainboard.asl A src/mainboard/asrock/imb-1222/acpi/sleep.asl A src/mainboard/asrock/imb-1222/board_info.txt A src/mainboard/asrock/imb-1222/bootblock.c A src/mainboard/asrock/imb-1222/cmos.default A src/mainboard/asrock/imb-1222/cmos.layout A src/mainboard/asrock/imb-1222/data.vbt A src/mainboard/asrock/imb-1222/devicetree.cb A src/mainboard/asrock/imb-1222/dsdt.asl A src/mainboard/asrock/imb-1222/gma-mainboard.ads A src/mainboard/asrock/imb-1222/gpio.c A src/mainboard/asrock/imb-1222/gpio_beep.c A src/mainboard/asrock/imb-1222/hda_verb.c A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h A src/mainboard/asrock/imb-1222/include/mainboard/superio.h A src/mainboard/asrock/imb-1222/panic.c A src/mainboard/asrock/imb-1222/ramstage.c A src/mainboard/asrock/imb-1222/romstage.c A src/mainboard/asrock/imb-1222/superio.c 24 files changed, 1,310 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/83107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Gerrit-Change-Number: 83107 Gerrit-PatchSet: 20 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Bao Zheng, Marshall Dawson, Matt DeVillier. Felix Held has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84233?usp=email ) Change subject: amdfwtool: Add combo new layout for new family ...................................................................... Patch Set 3: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84233/comment/54cf31a0_7d9d871a?us… : PS3, Line 1588: case PLATFORM_PHOENIX: i wonder if PLATFORM_GLINDA also has/needs this -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 22:11:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/kahlee: Add Kconfig to set IGD UMA allocation
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84235?usp=email ) Change subject: mb/google/kahlee: Add Kconfig to set IGD UMA allocation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Gerrit-Change-Number: 84235 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 22:04:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/kahlee: Add Kconfig to set IGD UMA allocation
by Matt DeVillier (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Matt DeVillier. Hello Felix Held, Jason Nien, Martin Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84235?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/kahlee: Add Kconfig to set IGD UMA allocation ...................................................................... mb/google/kahlee: Add Kconfig to set IGD UMA allocation Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/baseboard/devicetree.cb 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84235/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Gerrit-Change-Number: 84235 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
by Jérémy Compostella (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Eric Lai, Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84236?usp=email ) Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/84236/comment/21a66d23_1bc91e55?us… : PS1, Line 519: add %edx, %eax I find this a bit suspicous, let's take an example: with `CONFIG_DCACHE_RAM_SIZE` at 0x200000 and %ecx (way size) at 0x180000, %edx should be at 0x80000. If you add the remainder to the quotient, you get way count = %eax = 0x80001 isn't ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Gerrit-Change-Number: 84236 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 20:45:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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