coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
by Wentao Qin (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Jian Tong, wen zhang. Wentao Qin has posted comments on this change by Wentao Qin. ( https://review.coreboot.org/c/coreboot/+/84241?usp=email ) Change subject: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84241/comment/1adb09de_7863ddc1?us… : PS1, Line 17: lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. https://review.coreboot.org/c/coreboot/+/84241/comment/66e87a57_294f3786?us… : PS1, Line 24: lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/84241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Gerrit-Change-Number: 84241 Gerrit-PatchSet: 2 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 07:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
by Wentao Qin (Code Review) 07 Sep '24

07 Sep '24

Wentao Qin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84241?usp=email ) Change subject: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU ...................................................................... mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84241/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Gerrit-Change-Number: 84241 Gerrit-PatchSet: 2 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
by Wentao Qin (Code Review) 07 Sep '24

07 Sep '24

Wentao Qin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84241?usp=email ) Change subject: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU ...................................................................... mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lotso-rev0 ~ # lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84241/1 diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 85a3506..2970635 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -326,6 +326,7 @@ .clk_req = 0, .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" probe STORAGE STORAGE_NVME probe unprovisioned -- To view, visit https://review.coreboot.org/c/coreboot/+/84241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Gerrit-Change-Number: 84241 Gerrit-PatchSet: 1 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 90: (7 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/56aff37a_530ab5ce?us… : PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 > > @krishna.p.bhat.d@intel.com Please update the 21.0 ME spec. […] Sure, added to TODO bug. File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/a9f5aaba_4385cc99?us… : PS71, Line 367: config FSP_PUBLISH_MBP_HOB > note, those CLs are not merged yet, hence, you need to rebase your code later as well. Sure. File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/e183a2c0_fe679751?us… : PS37, Line 30: C_STATE_C0, /* 0 */ : C_STATE_C1, /* 1 */ : C_STATE_C1E, /* 2 */ : C_STATE_C6_SHORT_LAT, /* 3 */ : C_STATE_C6_LONG_LAT, /* 4 */ : C_STATE_C7_SHORT_LAT, /* 5 */ : C_STATE_C7_LONG_LAT, /* 6 */ : C_STATE_C7S_SHORT_LAT, /* 7 */ : C_STATE_C7S_LONG_LAT, /* 8 */ : C_STATE_C8, /* 9 */ : C_STATE_C9, /* 10 */ : C_STATE_C10, /* 11 */ : NUM_C_STATES > > Hi, I will be back on this info. Checking internally with the owners. […] Sure, added to TODO bug. File src/soc/intel/pantherlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/83798/comment/3e5ef259_e28273c4?us… : PS50, Line 15: > Hi,can we take up this to a crosbug, and mark TODO. Sure, added to TODO bug. File src/soc/intel/pantherlake/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/83798/comment/275cd37a_0876780e?us… : PS71, Line 7: #define C1_LATENCY 1 : #define C6_LATENCY 127 : #define C7_LATENCY 253 : #define C8_LATENCY 260 : #define C9_LATENCY 487 : #define C10_LATENCY 1048 > same Sure, added to TODO bug. https://review.coreboot.org/c/coreboot/+/83798/comment/4e36f095_5d41afe7?us… : PS71, Line 15: #define C1_POWER 0x3e8 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 > > please confirm the applicability and authenticity of these values for PTL SoC. […] Sure, added to TODO bug. File src/soc/intel/pantherlake/tcss.c: https://review.coreboot.org/c/coreboot/+/83798/comment/e8b2d0e2_1bd3b12f?us… : PS48, Line 6: const struct soc_tcss_ops tcss_ops = { > > Hi Subrata,we will be requiring this, since TCSS I/O Manager is above 4GB. […] Added to discuss more in TODO bug. Currently using skeleton code. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 90 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 05:40:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: src/device: Add more condition to check valid PCI device id
by Pratikkumar V Prajapati (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jeremy Compostella, Subrata Banik, Wonkyu Kim. Pratikkumar V Prajapati has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84228?usp=email ) Change subject: src/device: Add more condition to check valid PCI device id ...................................................................... Patch Set 2: (1 comment) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/84228/comment/f6a5406f_1faf5ecb?us… : PS2, Line 1225: dummy.vendor = id & 0xffff; : dummy.device = (id >> 16) & 0xffff; : if ((dummy.vendor == 0x0000) || (dummy.vendor == 0xffff) || : (dummy.device == 0x0000) || (dummy.device == 0xffff)) { : printk(BIOS_SPEW, "device %s [0x%04x/0x%04x] is not found.\n", : dev_path(&dummy), dummy.vendor, dummy.device); : why don't u make an inline function, as this test is used at multiple places? -- To view, visit https://review.coreboot.org/c/coreboot/+/84228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffabc9037a8af1b2a4ffebdf30199c4f6eae9540 Gerrit-Change-Number: 84228 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 04:52:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: src/intel/cmm/block: Update sa_get_tseg_size function
by Pratikkumar V Prajapati (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jeremy Compostella, Subrata Banik, Wonkyu Kim. Pratikkumar V Prajapati has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84210?usp=email ) Change subject: src/intel/cmm/block: Update sa_get_tseg_size function ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3d5175add1f7dc6e2c9f1c38133b36ffc59e789 Gerrit-Change-Number: 84210 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 04:46:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Doc/rmodules.md: Change header levels
by Nicholas Chin (Code Review) 06 Sep '24

06 Sep '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84239?usp=email ) Change subject: Doc/rmodules.md: Change header levels ...................................................................... Doc/rmodules.md: Change header levels Increase the header levels of headers following the initial "Relocatable Modules (rmodules)" so that there is only one title for the page with the other headings as subheadings. Also fix header capitalization while we're here. Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/rmodules.md 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/84239/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: Doc/rmodules.md: Move to technotes
by Nicholas Chin (Code Review) 06 Sep '24

06 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84240?usp=email ) Change subject: Doc/rmodules.md: Move to technotes ...................................................................... Doc/rmodules.md: Move to technotes The content of this page seems to fit the technote category the best, so move it. This also fixes a "document isn't included in any toctree" warning from Sphinx since it is now added to the technotes/index.md toctree. Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/technotes/index.md R Documentation/technotes/rmodules.md 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/84240/1 diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index e57519f..a787584 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -9,4 +9,5 @@ Unit Test Code Coverage <2021-05-code-coverage.md> Address Sanitizer <asan.md> coreboot Consoles <console.md> +Relocatable Modules <rmodules.md> ``` diff --git a/Documentation/rmodules.md b/Documentation/technotes/rmodules.md similarity index 100% rename from Documentation/rmodules.md rename to Documentation/technotes/rmodules.md -- To view, visit https://review.coreboot.org/c/coreboot/+/84240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Gerrit-Change-Number: 84240 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: Doc/rmodules.md: Fix header levels
by Nicholas Chin (Code Review) 06 Sep '24

06 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84239?usp=email ) Change subject: Doc/rmodules.md: Fix header levels ...................................................................... Doc/rmodules.md: Fix header levels Increase the header levels of headers following "Relocatable Modules (rmodules)" so that there is only one title and the other headings are subheadings of it. Also fix header capitalization while we're here. Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/rmodules.md 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/84239/1 diff --git a/Documentation/rmodules.md b/Documentation/rmodules.md index 520d184..39c72b6 100644 --- a/Documentation/rmodules.md +++ b/Documentation/rmodules.md @@ -15,9 +15,9 @@ based on the location of the binary (which was returned by CBMEM at runtime). -# Implementation Details +## Implementation Details -## build time +### Build Time At build time the rmodtool (util/cbfstool/rmodtool.c) is used to create relocatable modules. The rmodtool basically takes an ELF @@ -44,7 +44,7 @@ 2. program (.program) 3. relocation entries (.relocs) -## runtime +### Runtime Either rmodule\_load (lib/rmodule.c) is used directly or through the rmodule\_stage\_load (lib/rmodule.c) wrapper. It is used to load the @@ -59,7 +59,7 @@ itself is just a simple addition, that adds an offset from where the image was "supposed" to be at link time, to where it is now relocated. -## module\_parameters +### Module\_parameters module\_parameters is a section inside the rmodule ELF file. Its basically a way to pass runtime information to an rmodule @@ -73,7 +73,7 @@ struct smm_runtime smm_runtime; ``` -# x86 why rmodules +## x86 why rmodules //TODO x86: postcar and ramstage cannot conflict with payload regarding memory placement. Therefore payload location is usually fixed and -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax
by Nicholas Chin (Code Review) 06 Sep '24

06 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84238?usp=email ) Change subject: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax ...................................................................... Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks, not eval_rst as was previously used by recommonmark. Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/mainboard/starlabs/byte_adl.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/84238/1 diff --git a/Documentation/mainboard/starlabs/byte_adl.md b/Documentation/mainboard/starlabs/byte_adl.md index d357a5a..9683821 100644 --- a/Documentation/mainboard/starlabs/byte_adl.md +++ b/Documentation/mainboard/starlabs/byte_adl.md @@ -60,7 +60,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ -- To view, visit https://review.coreboot.org/c/coreboot/+/84238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Gerrit-Change-Number: 84238 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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coreboot-gerrit September 2024