coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
3342 discussions

[XS] Change in coreboot[main]: soc/intel: Add PCI DID for ADL-N (ID-6)
by Felix Held (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: David Milosevic. Felix Held has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/84215?usp=email ) Change subject: soc/intel: Add PCI DID for ADL-N (ID-6) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: just submitted CB:84212 which is a superset of this patch, so this one can be abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb87a5f2d28cb90b3c1cdcd50816bad6d873dddb Gerrit-Change-Number: 84215 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 15:43:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: soc/intel/{common,alderlake}: Add missing ADL-N SKUs
by Felix Held (Code Review) 07 Sep '24

07 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84212?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/{common,alderlake}: Add missing ADL-N SKUs ...................................................................... soc/intel/{common,alderlake}: Add missing ADL-N SKUs Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 111 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 481bf20..54fe0c1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4394,6 +4394,10 @@ #define PCI_DID_INTEL_ADL_N_ID_3 0x461c #define PCI_DID_INTEL_ADL_N_ID_4 0x4614 #define PCI_DID_INTEL_ADL_N_ID_5 0x4618 +#define PCI_DID_INTEL_ADL_N_ID_6 0x4678 +#define PCI_DID_INTEL_ADL_N_ID_7 0x4679 +#define PCI_DID_INTEL_ADL_N_ID_8 0x467C +#define PCI_DID_INTEL_ADL_N_ID_9 0x4677 #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 6372cd6..57e4f52 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -63,6 +63,10 @@ { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_6, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_7, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_8, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_9, "Alderlake-N" }, { PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" }, { PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c8005de..67d83b4 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -54,9 +54,13 @@ ADL_M_242_CORE, ADL_P_442_45W_CORE, ADL_N_081_7W_CORE, + ADL_N_081_9W_CORE, ADL_N_081_15W_CORE, ADL_N_041_6W_CORE, + ADL_N_041_12W_CORE, + ADL_N_041_15W_CORE, ADL_N_021_6W_CORE, + ADL_N_021_10W_CORE, ADL_S_882_35W_CORE, ADL_S_882_65W_CORE, ADL_S_882_125W_CORE, @@ -111,6 +115,7 @@ TDP_6W = 6, TDP_7W = 7, TDP_9W = 9, + TDP_10W = 10, TDP_12W = 12, TDP_15W = 15, TDP_28W = 28, @@ -148,12 +153,16 @@ { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, - { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W }, { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W }, + { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W }, + { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 0ab7c8a..7ae1990 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -54,6 +54,12 @@ .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_081_9W_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 35, @@ -66,12 +72,30 @@ .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_041_12W_CORE]" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_041_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + register "power_limits_config[ADL_N_021_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 25, .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_021_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 92b2532..255082f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -242,6 +242,10 @@ PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_5, + PCI_DID_INTEL_ADL_N_ID_6, + PCI_DID_INTEL_ADL_N_ID_7, + PCI_DID_INTEL_ADL_N_ID_8, + PCI_DID_INTEL_ADL_N_ID_9, }; const uint16_t rpl_hx_mch_ids[] = { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8dca5b0..8c4c291 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -596,6 +596,10 @@ case PCI_DID_INTEL_ADL_N_ID_3: case PCI_DID_INTEL_ADL_N_ID_4: case PCI_DID_INTEL_ADL_N_ID_5: + case PCI_DID_INTEL_ADL_N_ID_6: + case PCI_DID_INTEL_ADL_N_ID_7: + case PCI_DID_INTEL_ADL_N_ID_8: + case PCI_DID_INTEL_ADL_N_ID_9: return config->vccin_aux_imon_iccmax ? config->vccin_aux_imon_iccmax : ICC_MAX_ID_ADL_N_MA; case PCI_DID_INTEL_ADL_S_ID_1: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index c3584ba..95dba9f 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -123,11 +123,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -187,11 +193,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, @@ -251,11 +263,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -314,12 +332,18 @@ { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, - { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, + { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(17, 16) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, @@ -404,8 +428,10 @@ s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; } else { uint8_t tdp = get_cpu_tdp(); - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *gt = pcidev_path_on_root(SA_DEVFN_IGD); + uint16_t mch_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xffff; + uint16_t gt_id = gt ? pci_read_config16(gt, PCI_DEVICE_ID) : 0xffff; s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), domain, mch_id, tdp); @@ -419,6 +445,14 @@ s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, ARRAY_SIZE(vr_config_tdc_currentlimit), domain, mch_id, tdp); + + /* Exception: following ADL-N SKUs may have different GT TDC based on GT ID */ + if (mch_id == PCI_DID_INTEL_ADL_N_ID_2 || mch_id == PCI_DID_INTEL_ADL_N_ID_3) { + if (gt_id == PCI_DID_INTEL_ADL_N_GT1) + s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(20); + else if (gt_id == PCI_DID_INTEL_ADL_N_GT2) + s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(19); + } } fill_vr_fast_vmode(s_cfg, domain, chip_cfg); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 6239a46..3b71633 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -531,6 +531,10 @@ PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_5, + PCI_DID_INTEL_ADL_N_ID_6, + PCI_DID_INTEL_ADL_N_ID_7, + PCI_DID_INTEL_ADL_N_ID_8, + PCI_DID_INTEL_ADL_N_ID_9, PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, PCI_DID_INTEL_RPL_HX_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/84212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Gerrit-Change-Number: 84212 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: nb/intel/sandybridge: Add Kconfig to set default IGD allocation
by Felix Held (Code Review) 07 Sep '24

07 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84225?usp=email ) Change subject: nb/intel/sandybridge: Add Kconfig to set default IGD allocation ...................................................................... nb/intel/sandybridge: Add Kconfig to set default IGD allocation Add a Kconfig choice to select the default IGD memory allocation, for users/boards which do not use an option table to set it. TEST=build/boot google/link, verify IGD size changes with selection. Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84225 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c 2 files changed, 31 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index fa40b06..973eed8 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -180,4 +180,32 @@ config PRERAM_CBFS_CACHE_SIZE default 0x0 +choice + prompt "Default IGD Memory Allocation" + default IGD_DEFAULT_UMA_SIZE_32MB + help + The amount of system memory allocated for the integrated GPU if not + set via an option table. + +config IGD_DEFAULT_UMA_SIZE_32MB + bool "32MB" + +config IGD_DEFAULT_UMA_SIZE_64MB + bool "64MB" + +config IGD_DEFAULT_UMA_SIZE_96MB + bool "96MB" + +config IGD_DEFAULT_UMA_SIZE_128MB + bool "128MB" + +endchoice + +config IGD_DEFAULT_UMA_INDEX + int + default 0 if IGD_DEFAULT_UMA_SIZE_32MB + default 1 if IGD_DEFAULT_UMA_SIZE_64MB + default 2 if IGD_DEFAULT_UMA_SIZE_96MB + default 3 if IGD_DEFAULT_UMA_SIZE_128MB + endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a5ebf9d..1d8a1e8 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -86,9 +86,10 @@ printk(BIOS_DEBUG, "Initializing Graphics...\n"); - /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ - gfxsize = get_uint_option("gfx_uma_size", 0); + /* Fall back to CONFIG_IGD_DEFAULT_UMA_INDEX for IGD memory */ + gfxsize = get_uint_option("gfx_uma_size", CONFIG_IGD_DEFAULT_UMA_INDEX); + /* Program IGD memory allocation by setting GGC[7:3] */ reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; reg16 |= (gfxsize + 1) << 3; -- To view, visit https://review.coreboot.org/c/coreboot/+/84225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Gerrit-Change-Number: 84225 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Update touchscreen power sequence
by Felix Held (Code Review) 07 Sep '24

07 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84196?usp=email ) Change subject: mb/google/dedede/var/awasuki: Update touchscreen power sequence ...................................................................... mb/google/dedede/var/awasuki: Update touchscreen power sequence Reduce resume time. BUG=b:361728839 TEST=emerge-dedede coreboot chromeos-bootimage & test touchscreen function on awasuki DUT Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/awasuki/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index ad28296..6a7df2f 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -196,7 +196,6 @@ register "reset_off_delay_ms" = "8" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" - register "stop_delay_ms" = "280" register "stop_off_delay_ms" = "2" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" -- To view, visit https://review.coreboot.org/c/coreboot/+/84196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Gerrit-Change-Number: 84196 Gerrit-PatchSet: 4 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: amdfwtool: Set L2 table size as 0x400
by Felix Held (Code Review) 07 Sep '24

07 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84194?usp=email ) Change subject: amdfwtool: Set L2 table size as 0x400 ...................................................................... amdfwtool: Set L2 table size as 0x400 The Max size of L2 table is 0x400. If we set it to other value, the the A/B recovery image can not boot on Cezanne/Majolica platform. The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards are binary identical. Tested on Skyrim and image can boot. Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84194 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1fe9923..1d94e06 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -870,7 +870,7 @@ BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); - pspdir->entries[count].size = _MAX(TABLE_ALIGNMENT, + pspdir->entries[count].size = _MAX(TABLE_L2_SIZE_MAX, pspdir2->header.num_entries * sizeof(psp_directory_entry) + sizeof(psp_directory_header)); @@ -1216,11 +1216,11 @@ if (cb_config->recovery_ab) { add_psp_firmware_entry(ctx, ctx->pspdir2, ctx->biosdir2, - AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); + AMD_FW_BIOS_TABLE, TABLE_L2_SIZE_MAX); if (ctx->pspdir2_b != NULL) add_psp_firmware_entry(ctx, ctx->pspdir2_b, ctx->biosdir2_b, AMD_FW_BIOS_TABLE, - TABLE_ALIGNMENT); + TABLE_L2_SIZE_MAX); } else if (ctx->biosdir2) { current_table_save = ctx->current_table; ctx->current_table = BUFF_TO_RUN_MODE(*ctx, ctx->biosdir, AMD_ADDR_REL_BIOS); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index b2fd2c0..7ca7d89 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -11,6 +11,7 @@ #define ERASE_ALIGNMENT 0x1000U #define TABLE_ALIGNMENT 0x1000U +#define TABLE_L2_SIZE_MAX 0x400U #define BLOB_ALIGNMENT 0x100U #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) -- To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Gerrit-Change-Number: 84194 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB
by Matt DeVillier (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Jason Nien, Martin Roth. Hello Jason Nien, Martin Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84237?usp=email to look at the new patch set (#2). Change subject: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB ...................................................................... mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the corresponding UMA value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS as that is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/zork/Kconfig D src/mainboard/google/zork/data.apcb M src/mainboard/google/zork/spd/Makefile.mk A src/mainboard/google/zork/uma_128.apcb A src/mainboard/google/zork/uma_256.apcb A src/mainboard/google/zork/uma_512.apcb A src/mainboard/google/zork/uma_64.apcb 7 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84237/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Gerrit-Change-Number: 84237 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

1 0

[L] Change in coreboot[main]: ec/hp/kbc1126/acpi: Document EC RAM fields
by Nicholas Sudsgaard (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Iru Cai. Hello Iru Cai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84242?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: ec/hp/kbc1126/acpi: Document EC RAM fields ...................................................................... ec/hp/kbc1126/acpi: Document EC RAM fields This is not perfect, as documentation for some fields are missing or speculative. However, I think it is enough to be a good starting point. This was done by only analyzing the ACPI dump from vendor firmware, we could understand more by looking deeper into the vendor firmware, but this would take more time and effort. I'll leave that as a task for me or somebody else in the future. Change-Id: Ic411a7a821d7b03be45d4bda645a03f82c7241c5 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/ec/hp/kbc1126/acpi/ac.asl M src/ec/hp/kbc1126/acpi/battery.asl M src/ec/hp/kbc1126/acpi/ec.asl 3 files changed, 178 insertions(+), 149 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84242/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic411a7a821d7b03be45d4bda645a03f82c7241c5 Gerrit-Change-Number: 84242 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com>

1 0

[XS] Change in coreboot[main]: Doc/rmodules.md: Move to technotes
by Nico Huber (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84240?usp=email ) Change subject: Doc/rmodules.md: Move to technotes ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: I'd rather not. This seems to become a sinkhole for coreboot guides and concepts while it actually started very differently? Looking through the TOC, I noticed `Libraries` right now. I would have guessed to find APIs there, but given its contents it might actually fit `rmodules` as well. After only a superficial look, I'd say `asan` and `console` are more like guides? And everything in `Libraries` plus `rmodules` are concepts/architecture? Also, it seems to me that initially people just ordered things by the source directories. At least that would explain `Libraries` to me. Maybe it's time to discuss what top-level categories we actually want to have. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/84240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Gerrit-Change-Number: 84240 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 09:35:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: Doc/rmodules.md: Change header levels
by Nico Huber (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84239?usp=email ) Change subject: Doc/rmodules.md: Change header levels ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File Documentation/rmodules.md: https://review.coreboot.org/c/coreboot/+/84239/comment/0bbb8533_eeeb60ac?us… : PS2, Line 62: ### Module\_parameters Given that it's also written lower-case in the text (and supposed to match code, i guess), I'd leave this lower-case, WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 09:20:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax
by Nico Huber (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84238?usp=email ) Change subject: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Gerrit-Change-Number: 84238 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Sep 2024 09:14:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2024