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Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/84236/comment/6c1b2b3b_66807089?us… :
PS1, Line 519: add %edx, %eax
> I find this a bit suspicous, let's take an example: with `CONFIG_DCACHE_RAM_SIZE` at 0x200000 and %ecx (way size) at 0x180000, %edx should be at 0x80000. If you add the remainder to the quotient, you get way count = %eax = 0x80001 isn't ?
for sure, I missed adding the `testl` logic to check if EDX is zero or not before incrementing the quotient.
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Change subject: amdfwtool: Add combo new layout for new family
......................................................................
amdfwtool: Add combo new layout for new family
The new layout definition has a new way to support combo.
It packs multiple ISH entries into PSP L1 directory.
TEST=Identical test on all AMD platform
Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 30 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/5
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Change subject: amdfwtool: Add combo new layout for new family
......................................................................
Patch Set 4:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84233/comment/c004743f_d1cd6966?us… :
PS3, Line 1588: case PLATFORM_PHOENIX:
> i wonder if PLATFORM_GLINDA also has/needs this
I believe when it needs ish, it needs new combo layout.
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Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84195/comment/819c93f4_b11e3dba?us… :
PS3, Line 22: /disable
> Sorry but I believe the commit message should read "passed to amdfwtool to enable...".
Done
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Change subject: amdfwtool: Add combo new layout for new family
......................................................................
amdfwtool: Add combo new layout for new family
The new layout definition has a new way to support combo.
It packs multiple ISH entries into PSP L1 directory.
TEST=Identical test on all AMD platform
Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/4
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Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme
......................................................................
soc/amd/cezanne: Add an option to enable A/B recovery scheme
Extracted from NDA spec #56995:
"The A/B recovery scheme formally separates the SPI flash space into
different partitions; a primary, “A” and secondary, “B”, which hold
the same set of system firmware. Under this scheme, the partitions A
and B can hold identical contents initially, but each partition can be
updated individually.
Normally the system boots from partition A, but if the A partition is
found to be corrupted, the system will switch to partition B and
boot. The OEM BIOS can then choose to continue the boot from partition
B, or repair partition A using contents from partition B."
The Cezanne platform supports both A/B recovery and no recovery
method. It needs this flag passed to amdfwtool to enable the A/B
recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.mk
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/5
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Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
......................................................................
Patch Set 2:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/84221/comment/03cc1344_4c416ec3?us… :
PS1, Line 37: val_regs
> Can we rename it to `gpio_val_regs`?
Done
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Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
......................................................................
soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
BUG=none
TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot
Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
A src/soc/mediatek/common/include/soc/gpio_defs.h
M src/soc/mediatek/mt8186/include/soc/gpio.h
M src/soc/mediatek/mt8188/include/soc/gpio.h
M src/soc/mediatek/mt8192/include/soc/gpio.h
M src/soc/mediatek/mt8195/include/soc/gpio.h
M src/soc/mediatek/mt8196/include/soc/gpio.h
6 files changed, 69 insertions(+), 199 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/84221/2
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 8:
(1 comment)
File payloads/libpayload/configs/defconfig_64:
https://review.coreboot.org/c/coreboot/+/84107/comment/1209f834_715b1e89?us… :
PS8, Line 1: # NOTE: remove to test _LP64 issue: CONFIG_LP_ARCH_X86_64=y
> If CONFIG_LP_ARCH_X86_64=y is included, we will run into the issue shown in https://qa.coreboot. […]
If this is commented out it's same as defconfig.
Can it be related to below make file?
payloads/libpayload/curses/Makefile.mk:41:INCLUDES += -D_LP64=0 -Icurses/$(PDCURSES) -Icurses/pdcurses-backend -Icurses/menu -Icurses/form
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