coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 91: (1 comment) File src/soc/intel/pantherlake/tcss.c: https://review.coreboot.org/c/coreboot/+/83798/comment/4b049048_eb8d5f8a?us… : PS91, Line 12: ioe_tcss_valid_tbt_auth who is the consumer of this code now ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 91 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 05:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#92). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h M src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 42 files changed, 3,725 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/92 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 92 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#91). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h M src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 42 files changed, 3,720 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/91 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 91 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 90: (1 comment) File src/soc/intel/pantherlake/tcss.c: https://review.coreboot.org/c/coreboot/+/83798/comment/8441fedb_9a13c771?us… : PS48, Line 6: const struct soc_tcss_ops tcss_ops = { > > Added to discuss more in TODO bug. Currently using skeleton code. […] Sure, implemented as suggested. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 90 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 04:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: Docs: Revert false MyST Parser toctree conversions
by Nicholas Chin (Code Review) 08 Sep '24

08 Sep '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84244?usp=email ) Change subject: Docs: Revert false MyST Parser toctree conversions ...................................................................... Docs: Revert false MyST Parser toctree conversions Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser) converted recommonmark style toctrees in bulk using a script. This was done by searching for lists of references, which is how recommonmark denoted toctree entries. However, this also converted lists of external URLs, which would not normally be included in the toctree. Revert these cases back to lists of URLs as they were before the migration. Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/kconfig.md M Documentation/infrastructure/builders.md M Documentation/mainboard/lenovo/ivb_internal_flashing.md M Documentation/mainboard/protectli/vp2420.md M Documentation/mainboard/protectli/vp46xx.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/technotes/console.md 14 files changed, 54 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84244/1 diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md index 15d3ddd..4337611 100644 --- a/Documentation/acpi/index.md +++ b/Documentation/acpi/index.md @@ -29,10 +29,6 @@ ## ACPI specification - Useful links -```{toctree} -:maxdepth: 1 - -ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html> -ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-oper…> -Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#pre…> -``` +- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html) +- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbo… +- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.h… diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 8dbb067..2f32b85 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -1141,8 +1141,4 @@ ## References: -```{toctree} -:maxdepth: 1 - -AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-w…> -``` +* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-2022050… diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md index d68e51c..c9f0060 100644 --- a/Documentation/drivers/smmstore.md +++ b/Documentation/drivers/smmstore.md @@ -128,11 +128,8 @@ ## External links -```{toctree} -:maxdepth: 1 +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… -A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_…> -``` Note, this differs significantly from coreboot's implementation. [SMM]: ../security/smm.md diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 8e74c93..6956cd4 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -199,11 +199,8 @@ ## External links -```{toctree} -:maxdepth: 1 +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… -A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_…> -``` Note that this differs significantly from coreboot's implementation. [SMM]: ../security/smm.md diff --git a/Documentation/external_docs.md b/Documentation/external_docs.md index 47c7600..b5ee908 100644 --- a/Documentation/external_docs.md +++ b/Documentation/external_docs.md @@ -17,21 +17,13 @@ * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-in… * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-in… * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_bu… -```{toctree} -:maxdepth: 1 - -Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html> -``` +* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html) ## General Information -```{toctree} -:maxdepth: 1 - -OS Dev <https://wiki.osdev.org/Categorized_Main_Page> -Interface BUS <http://www.interfacebus.com/> -``` +* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page) +* [Interface BUS](http://www.interfacebus.com/) ## OpenSecurityTraining2 @@ -51,14 +43,10 @@ Below is a list of currently available courses that can help understand the inner workings of coreboot and other firmware-related topics: -```{toctree} -:maxdepth: 1 - -coreboot design principles and boot process <https://ost2.fyi/Arch4031> -x86-64 Assembly <https://ost2.fyi/Arch1001> -x86-64 OS Internals <https://ost2.fyi/Arch2001> -x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001> -``` +* [coreboot design principles and boot process](https://ost2.fyi/Arch4031) +* [x86-64 Assembly](https://ost2.fyi/Arch1001) +* [x86-64 OS Internals](https://ost2.fyi/Arch2001) +* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001) There are [additional security courses](https://p.ost2.fyi/courses) at the site as well (such as @@ -66,79 +54,47 @@ ## Firmware Specifications & Information -```{toctree} -:maxdepth: 1 - -System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios> -Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash> -PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desk…> -``` +* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios) +* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash) +* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboard… ### ACPI -```{toctree} -:maxdepth: 1 - -ACPI Specs <https://uefi.org/acpi/specs> -ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf> -ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-…> -ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_L…> -``` +* [ACPI Specs](https://uefi.org/acpi/specs) +* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf) +* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/L… +* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_… ### Security -```{toctree} -:maxdepth: 1 - -Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secur…> -``` +* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard) ## Hardware information -```{toctree} -:maxdepth: 1 - -WikiChip <https://en.wikichip.org/wiki/WikiChip> -Sandpile <https://www.sandpile.org/> -CPU-World <https://www.cpu-world.com/index.html> -CPU-Upgrade <https://www.cpu-upgrade.com/index.html> -``` +* [WikiChip](https://en.wikichip.org/wiki/WikiChip) +* [Sandpile](https://www.sandpile.org/) +* [CPU-World](https://www.cpu-world.com/index.html) +* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html) ### Hardware Specifications & Standards * [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG -```{toctree} -:maxdepth: 1 - -eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> -``` +* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) * [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel * [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/e…, [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP * [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP -```{toctree} -:maxdepth: 1 - -I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED> -Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> -``` +* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED) +* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) * [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications * [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/l… - Intel -```{toctree} -:maxdepth: 1 - -PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED> -``` +* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED) * [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum -```{toctree} -:maxdepth: 1 - -SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED> -``` +* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED) * [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum * [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum * [USB](https://www.usb.org/documents) - USB Implementers Forum @@ -177,9 +133,5 @@ ## Infrastructure software -```{toctree} -:maxdepth: 1 - -Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html> -GNU Make <https://www.gnu.org/software/make/manual/> -``` +* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.htm… +* [GNU Make](https://www.gnu.org/software/make/manual/) diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index bff077c..8965458 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -11,12 +11,8 @@ The official Kconfig source and documentation is kept at kernel.org: -```{toctree} -:maxdepth: 1 - -Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/script…> -Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt> -``` +- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tre… +- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-lang… The advantage to using Kconfig is that it allows users to easily select the high level features of the project to be enabled or disabled at build time. diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md index dc4216d..b200140e 100644 --- a/Documentation/infrastructure/builders.md +++ b/Documentation/infrastructure/builders.md @@ -93,19 +93,11 @@ Most of the time on the builders is taken up by the coreboot main and coreboot gerrit builds. -```{toctree} -:maxdepth: 1 - -coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/> -``` +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) -```{toctree} -:maxdepth: 1 - -coreboot main build <https://qa.coreboot.org/job/coreboot/> -``` +* [coreboot main build](https://qa.coreboot.org/job/coreboot/) ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index a6004a7..3559481 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -19,11 +19,7 @@ - USB drive (in case you need to downgrade BIOS) - Linux install that (can be) loaded in UEFI mode -```{toctree} -:maxdepth: 1 - -CHIPSEC <https://github.com/chipsec/chipsec> -``` +- [CHIPSEC](https://github.com/chipsec/chipsec) ## BIOS versions diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md index b5a7ff6..b4ec597 100644 --- a/Documentation/mainboard/protectli/vp2420.md +++ b/Documentation/mainboard/protectli/vp2420.md @@ -80,12 +80,8 @@ ## Useful links -```{toctree} -:maxdepth: 1 - -VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/> -VP2420 Product Page <https://protectli.com/product/vp2420/> -Protectli TPM module <https://protectli.com/product/tpm-module/> -MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,…> -flashrom <https://flashrom.org/Flashrom> -``` +- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/) +- [VP2420 Product Page](https://protectli.com/product/vp2420/) +- [Protectli TPM module](https://protectli.com/product/tpm-module/) +- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf) +- [flashrom](https://flashrom.org/Flashrom) diff --git a/Documentation/mainboard/protectli/vp46xx.md b/Documentation/mainboard/protectli/vp46xx.md index eada7ff..f86f931 100644 --- a/Documentation/mainboard/protectli/vp46xx.md +++ b/Documentation/mainboard/protectli/vp46xx.md @@ -126,13 +126,9 @@ ## Useful links -```{toctree} -:maxdepth: 1 - -VP4600 Hardware Overview <https://protectli.com/kb/vp4600-hardware-overview/> -VP4630 Product Page <https://protectli.com/product/vp4630/> -Protectli TPM module <https://protectli.com/product/tpm-module/> -``` +- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/) +- [VP4630 Product Page](https://protectli.com/product/vp4630/) +- [Protectli TPM module](https://protectli.com/product/tpm-module/) [Protectli VP46xx]: https://protectli.com/vault-6-port/ [MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,… diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md index 2ad45ca..eb136f4 100644 --- a/Documentation/releases/coreboot-4.17-relnotes.md +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -12,11 +12,7 @@ Major Bugfixes in this release ------------------------------ -```{toctree} -:maxdepth: 1 - -CVE-2022-29264 <https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264> -``` +* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-292… New Mainboards diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index d2629b4..b7dbc5f 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -56,9 +56,5 @@ ## References -```{toctree} -:maxdepth: 1 - -Intel TXT LAB handout <https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf> -FIT BIOS specification <https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bio…> -``` +* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Han… +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents… diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md index bb14af0..6d7afb4 100644 --- a/Documentation/soc/intel/fsp/ppi/ppi.md +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -6,17 +6,9 @@ where FSP should be able to locate PPI, published by boot firmware and able to execute the same in FSP's context. -```{toctree} -:maxdepth: 1 - -What is PPI <https://www.intel.com/content/dam/www/public/us/en/documents/reference-guid…> -``` +* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference… ## List of PPI service ### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU -```{toctree} -:maxdepth: 1 - -MP Service PPI <mp_service_ppi.md> -``` +- [MP Service PPI](mp_service_ppi.md) diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md index 1b022a2..a125728 100644 --- a/Documentation/technotes/console.md +++ b/Documentation/technotes/console.md @@ -57,18 +57,10 @@ If not we can use other I2C slave devices like an Arduino or a Beagleboard. -```{toctree} -:maxdepth: 1 - -Linux I2C Slave interface <https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/…> -BeagleBone Black I2C Slave <https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/…> -``` +* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.or… +* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard… This feature was added as part of a GSoC 2022 project. Checkout the following blog posts for more details. -```{toctree} -:maxdepth: 1 - -coreboot Console via SMBus — Part I <https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273…> -coreboot Console via SMBus — Part II <https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f…> -``` +* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38… +* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324f… -- To view, visit https://review.coreboot.org/c/coreboot/+/84244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Gerrit-Change-Number: 84244 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: amdfwtool: Add combo new layout for new family
by Bao Zheng (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Felix Held, Marshall Dawson, Matt DeVillier. Hello Felix Held, Marshall Dawson, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84233?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Add combo new layout for new family ...................................................................... amdfwtool: Add combo new layout for new family The new layout definition has a new way to support combo. It packs multiple ISH entries into PSP L1 directory. TEST=Identical test on all AMD platform Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 30 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Gerrit-Change-Number: 84233 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/kahlee: Add Kconfig to set IGD UMA allocation
by Felix Held (Code Review) 08 Sep '24

08 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84235?usp=email ) Change subject: mb/google/kahlee: Add Kconfig to set IGD UMA allocation ...................................................................... mb/google/kahlee: Add Kconfig to set IGD UMA allocation Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/baseboard/devicetree.cb 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 86632db..60630fe 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -172,4 +172,31 @@ default n if CHROMEOS default y +choice + prompt "UMA Memory Allocation" + default KAHLEE_UMA_SIZE_32MB + help + The amount of system memory allocated for the integrated GPU + +config KAHLEE_UMA_SIZE_32MB + bool "32MB" + +config KAHLEE_UMA_SIZE_64MB + bool "64MB" + +config KAHLEE_UMA_SIZE_128MB + bool "128MB" + +config KAHLEE_UMA_SIZE_256MB + bool "256MB" + +endchoice + +config UMA_SIZE_IN_MB + int + default 32 if KAHLEE_UMA_SIZE_32MB + default 64 if KAHLEE_UMA_SIZE_64MB + default 128 if KAHLEE_UMA_SIZE_128MB + default 256 if KAHLEE_UMA_SIZE_256MB + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index ef7839d..ca8933a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -8,7 +8,7 @@ }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "CONFIG_UMA_SIZE_IN_MB * MiB" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" -- To view, visit https://review.coreboot.org/c/coreboot/+/84235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Gerrit-Change-Number: 84235 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB
by Felix Held (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84237?usp=email ) Change subject: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Gerrit-Change-Number: 84237 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 00:24:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 07 Sep '24

07 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... soc/intel/ptl: Add GPIOs for Panther Lake SOC Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO ref doc: - PT EDS vol2 - Panther Lake H GPIO Implementation Summary (#817954) BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/gpio.c A src/soc/intel/pantherlake/include/soc/gpio.h A src/soc/intel/pantherlake/include/soc/gpio_defs.h A src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h 5 files changed, 1,069 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index 477a5d7..2704305 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -10,9 +10,11 @@ bootblock-y += bootblock/pcd.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c +bootblock-y += gpio.c bootblock-y += soc_info.c romstage-y += espi.c +romstage-y += gpio.c romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c diff --git a/src/soc/intel/pantherlake/gpio.c b/src/soc/intel/pantherlake/gpio.c new file mode 100644 index 0000000..581607d --- /dev/null +++ b/src/soc/intel/pantherlake/gpio.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, + { .logical = PAD_RESET(GLBRST), .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Panther Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + */ +static const struct pad_group ptl_community0_groups[] = { + INTEL_GPP_BASE(GPP_V00, GPP_V00, GPP_RST_B, 0), /* GPP_V */ + INTEL_GPP_BASE(GPP_V00, GPP_C00, GPP_C23, 32), /* GPP_C */ +}; + +static const struct pad_group ptl_community1_groups[] = { + INTEL_GPP_BASE(GPP_F00, GPP_F00, GPP_GSPI0_CLK_LOOPBK, 0), /* GPP_F */ + INTEL_GPP_BASE(GPP_F00, GPP_E00, GPP_THC0_GSPI_CLK_LPBK, 32), /* GPP_E */ +}; + +static const struct pad_group ptl_community3_groups[] = { + INTEL_GPP(GPP_EPD_ON, GPP_EPD_ON, GPP_DDSP_HPDALV), /* GPP_CPUJTAG */ + INTEL_GPP_BASE(GPP_EPD_ON, GPP_H00, GPP_ISHI3C1_CLK_LPBK, 32), /* GPP_H */ + INTEL_GPP_BASE(GPP_EPD_ON, GPP_A00, GPP_SPI0_CLK_LOOPBK, 64), /* GPP_A */ + INTEL_GPP(GPP_EPD_ON, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3), /* GPP_VGPIO_3*/ +}; + +static const struct pad_group ptl_community4_groups[] = { + INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 0), /* GPP_S */ +}; + +static const struct pad_group ptl_community5_groups[] = { + INTEL_GPP_BASE(GPP_B00, GPP_B00, GPP_ISHI3C0_CLK_LPBK, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B00, GPP_D00, GPP_D25, 32), /* GPP_D */ + INTEL_GPP(GPP_B00, GPP_VGPIO0, GPP_VGPIO47), /* GPP_VGPIO */ +}; + +static const struct pad_community ptl_communities[] = { + [COMM_0] = { /* GPP V,C */ + .port = PID_GPIOCOM0, + .first_pad = COM0_GRP_PAD_START, + .last_pad = COM0_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_V_C", + .acpi_path = "\\_SB.PCI0.GPI0", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ptl_community0_groups, + .num_groups = ARRAY_SIZE(ptl_community0_groups), + }, + [COMM_1] = { /* GPP: F, E */ + .port = PID_GPIOCOM1, + .first_pad = COM1_GRP_PAD_START, + .last_pad = COM1_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_F_E", + .acpi_path = "\\_SB.PCI0.GPI1", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ptl_community1_groups, + .num_groups = ARRAY_SIZE(ptl_community1_groups), + }, + [COMM_3] = { /* GPP: CPUJTAG, H, A, VGPIO3 */ + .port = PID_GPIOCOM3, + .first_pad = COM3_GRP_PAD_START, + .last_pad = COM3_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPUJTAG_H_A_VGPIO3", + .acpi_path = "\\_SB.PCI0.GPI3", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ptl_community3_groups, + .num_groups = ARRAY_SIZE(ptl_community3_groups), + }, + [COMM_4] = { /* GPP: S */ + .port = PID_GPIOCOM4, + .first_pad = COM4_GRP_PAD_START, + .last_pad = COM4_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_S", + .acpi_path = "\\_SB.PCI0.GPI4", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ptl_community4_groups, + .num_groups = ARRAY_SIZE(ptl_community4_groups), + }, + [COMM_5] = { /* GPP: B, D, VGPIO */ + .port = PID_GPIOCOM5, + .first_pad = COM5_GRP_PAD_START, + .last_pad = COM5_GRP_PAD_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, + .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_B_D_VGPIO", + .acpi_path = "\\_SB.PCI0.GPI5", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ptl_community5_groups, + .num_groups = ARRAY_SIZE(ptl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(ptl_communities); + return ptl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_V, GPP_V }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_VGPIO, GPP_VGPIO }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/pantherlake/include/soc/gpio.h b/src/soc/intel/pantherlake/include/soc/gpio.h new file mode 100644 index 0000000..d7b562f --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/gpio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_GPIO_H_ +#define _SOC_PANTHERLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#define CROS_GPIO_NAME "INTC10BC" +#define CROS_GPIO_DEVICE0_NAME "INTC10BC:00" +#define CROS_GPIO_DEVICE1_NAME "INTC10BC:01" +#define CROS_GPIO_DEVICE2_NAME "INTC10BC:02" +#define CROS_GPIO_DEVICE3_NAME "INTC10BC:03" +#define CROS_GPIO_DEVICE4_NAME "INTC10BC:04" + +#define ACPI_GPIO_CID "INTC105F" +#define ACPI_GPIO_HID CROS_GPIO_NAME + +#define GPP_COMM0_NAME "Community 0" +#define GPP_COMM1_NAME "Community 1" +#define GPP_COMM3_NAME "Community 3" +#define GPP_COMM4_NAME "Community 4" +#define GPP_COMM5_NAME "Community 5" + +/* Enable GPIO community power management configuration */ +#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \ + MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ + | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + +#endif //_SOC_PANTHERLAKE_GPIO_H_ diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..e9fdc46 --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_GPIO_DEFS_H_ +#define _SOC_PANTHERLAKE_GPIO_DEFS_H_ + +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM0_GRP_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM1_GRP_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM3_GRP_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM4_GRP_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM5_GRP_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group V */ +#define GPP_V00_IRQ 0x18 +#define GPP_V01_IRQ 0x19 +#define GPP_V02_IRQ 0x1A +#define GPP_V03_IRQ 0x1B +#define GPP_V04_IRQ 0x1C +#define GPP_V05_IRQ 0x1D +#define GPP_V06_IRQ 0x1E +#define GPP_V07_IRQ 0x1F +#define GPP_V08_IRQ 0x20 +#define GPP_V09_IRQ 0x21 +#define GPP_V10_IRQ 0x22 +#define GPP_V11_IRQ 0x23 +#define GPP_V12_IRQ 0x24 +#define GPP_V13_IRQ 0x25 +#define GPP_V14_IRQ 0x26 +#define GPP_V15_IRQ 0x27 +#define GPP_V16_IRQ 0x28 +#define GPP_V17_IRQ 0x29 + +/* Group C */ +#define GPP_C00_IRQ 0x2A +#define GPP_C01_IRQ 0x2B +#define GPP_C02_IRQ 0x2C +#define GPP_C03_IRQ 0x2D +#define GPP_C04_IRQ 0x2E +#define GPP_C05_IRQ 0x2F +#define GPP_C06_IRQ 0x30 +#define GPP_C07_IRQ 0x31 +#define GPP_C08_IRQ 0x32 +#define GPP_C09_IRQ 0x33 +#define GPP_C10_IRQ 0x34 +#define GPP_C11_IRQ 0x35 +#define GPP_C12_IRQ 0x36 +#define GPP_C13_IRQ 0x37 +#define GPP_C14_IRQ 0x38 +#define GPP_C15_IRQ 0x39 +#define GPP_C16_IRQ 0x3A +#define GPP_C17_IRQ 0x3B +#define GPP_C18_IRQ 0x3C +#define GPP_C19_IRQ 0x3D +#define GPP_C20_IRQ 0x3E +#define GPP_C21_IRQ 0x3F +#define GPP_C22_IRQ 0x40 +#define GPP_C23_IRQ 0x41 + +/* Group F */ +#define GPP_F00_IRQ 0x42 +#define GPP_F01_IRQ 0x43 +#define GPP_F02_IRQ 0x44 +#define GPP_F03_IRQ 0x45 +#define GPP_F04_IRQ 0x46 +#define GPP_F05_IRQ 0x47 +#define GPP_F06_IRQ 0x48 +#define GPP_F07_IRQ 0x49 +#define GPP_F08_IRQ 0x4A +#define GPP_F09_IRQ 0x4B +#define GPP_F10_IRQ 0x4C +#define GPP_F11_IRQ 0x4D +#define GPP_F12_IRQ 0x4E +#define GPP_F13_IRQ 0x4F +#define GPP_F14_IRQ 0x50 +#define GPP_F15_IRQ 0x51 +#define GPP_F16_IRQ 0x52 +#define GPP_F17_IRQ 0x53 +#define GPP_F18_IRQ 0x54 +#define GPP_F19_IRQ 0x55 +#define GPP_F20_IRQ 0x56 +#define GPP_F21_IRQ 0x57 +#define GPP_F22_IRQ 0x58 +#define GPP_F23_IRQ 0x59 + +/* Group E */ +#define GPP_E00_IRQ 0x5A +#define GPP_E01_IRQ 0x5B +#define GPP_E02_IRQ 0x5C +#define GPP_E03_IRQ 0x5D +#define GPP_E04_IRQ 0x5E +#define GPP_E05_IRQ 0x5F +#define GPP_E06_IRQ 0x60 +#define GPP_E07_IRQ 0x61 +#define GPP_E08_IRQ 0x62 +#define GPP_E09_IRQ 0x63 +#define GPP_E10_IRQ 0x64 +#define GPP_E11_IRQ 0x65 +#define GPP_E12_IRQ 0x66 +#define GPP_E13_IRQ 0x67 +#define GPP_E14_IRQ 0x68 +#define GPP_E15_IRQ 0x69 +#define GPP_E16_IRQ 0x6A +#define GPP_E17_IRQ 0x6B +#define GPP_E18_IRQ 0x6C +#define GPP_E19_IRQ 0x6D +#define GPP_E20_IRQ 0x6E +#define GPP_E21_IRQ 0x6F +#define GPP_E22_IRQ 0x70 + +/* Group H */ +#define GPP_H00_IRQ 0x23 +#define GPP_H01_IRQ 0x24 +#define GPP_H02_IRQ 0x25 +#define GPP_H03_IRQ 0x26 +#define GPP_H04_IRQ 0x27 +#define GPP_H05_IRQ 0x28 +#define GPP_H06_IRQ 0x29 +#define GPP_H07_IRQ 0x2A +#define GPP_H08_IRQ 0x2B +#define GPP_H09_IRQ 0x2C +#define GPP_H10_IRQ 0x2D +#define GPP_H11_IRQ 0x2E +#define GPP_H12_IRQ 0x2F +#define GPP_H13_IRQ 0x30 +#define GPP_H14_IRQ 0x31 +#define GPP_H15_IRQ 0x32 +#define GPP_H16_IRQ 0x33 +#define GPP_H17_IRQ 0x34 +#define GPP_H18_IRQ 0x35 +#define GPP_H19_IRQ 0x36 +#define GPP_H20_IRQ 0x37 +#define GPP_H21_IRQ 0x38 +#define GPP_H22_IRQ 0x39 +#define GPP_H23_IRQ 0x3A +#define GPP_H24_IRQ 0x3B + +/* Group A */ +#define GPP_A00_IRQ 0x71 +#define GPP_A01_IRQ 0x72 +#define GPP_A02_IRQ 0x73 +#define GPP_A03_IRQ 0x74 +#define GPP_A04_IRQ 0x75 +#define GPP_A05_IRQ 0x76 +#define GPP_A06_IRQ 0x77 +#define GPP_A07_IRQ 0x18 +#define GPP_A08_IRQ 0x19 +#define GPP_A09_IRQ 0x1A +#define GPP_A10_IRQ 0x1B +#define GPP_A11_IRQ 0x1C +#define GPP_A12_IRQ 0x1D +#define GPP_A13_IRQ 0x1E +#define GPP_A14_IRQ 0x1F +#define GPP_A15_IRQ 0x20 +#define GPP_A16_IRQ 0x21 +#define GPP_A17_IRQ 0x22 + +/* Group B */ +#define GPP_B00_IRQ 0x42 +#define GPP_B01_IRQ 0x43 +#define GPP_B02_IRQ 0x44 +#define GPP_B03_IRQ 0x45 +#define GPP_B04_IRQ 0x46 +#define GPP_B05_IRQ 0x47 +#define GPP_B06_IRQ 0x48 +#define GPP_B07_IRQ 0x49 +#define GPP_B08_IRQ 0x4A +#define GPP_B09_IRQ 0x4B +#define GPP_B10_IRQ 0x4C +#define GPP_B11_IRQ 0x4D +#define GPP_B12_IRQ 0x4E +#define GPP_B13_IRQ 0x4F +#define GPP_B14_IRQ 0x50 +#define GPP_B15_IRQ 0x51 +#define GPP_B16_IRQ 0x52 +#define GPP_B17_IRQ 0x53 +#define GPP_B18_IRQ 0x54 +#define GPP_B19_IRQ 0x55 +#define GPP_B20_IRQ 0x56 +#define GPP_B21_IRQ 0x57 +#define GPP_B22_IRQ 0x58 +#define GPP_B23_IRQ 0x59 +#define GPP_B24_IRQ 0x5A +#define GPP_B25_IRQ 0x5B + +/* Group D */ +#define GPP_D00_IRQ 0x5C +#define GPP_D01_IRQ 0x5D +#define GPP_D02_IRQ 0x5E +#define GPP_D03_IRQ 0x5F +#define GPP_D04_IRQ 0x60 +#define GPP_D05_IRQ 0x61 +#define GPP_D06_IRQ 0x62 +#define GPP_D07_IRQ 0x63 +#define GPP_D08_IRQ 0x64 +#define GPP_D09_IRQ 0x65 +#define GPP_D10_IRQ 0x66 +#define GPP_D11_IRQ 0x67 +#define GPP_D12_IRQ 0x68 +#define GPP_D13_IRQ 0x69 +#define GPP_D14_IRQ 0x6A +#define GPP_D15_IRQ 0x6B +#define GPP_D16_IRQ 0x6C +#define GPP_D17_IRQ 0x6D +#define GPP_D18_IRQ 0x6E +#define GPP_D19_IRQ 0x6F +#define GPP_D20_IRQ 0x70 +#define GPP_D21_IRQ 0x71 +#define GPP_D22_IRQ 0x72 +#define GPP_D23_IRQ 0x73 +#define GPP_D24_IRQ 0x74 +#define GPP_D25_IRQ 0x75 + +/* Group S */ +#define GPP_S00_IRQ 0x19 +#define GPP_S01_IRQ 0x1A +#define GPP_S02_IRQ 0x1B +#define GPP_S03_IRQ 0x1C +#define GPP_S04_IRQ 0x1D +#define GPP_S05_IRQ 0x1E +#define GPP_S06_IRQ 0x1F +#define GPP_S07_IRQ 0x20 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define PAD_OWN_REG_0 0x130 +#define PAD_CFG_LOCK_REG_0 0x290 +#define HOSTSW_OWN_REG_0 0x2c0 +#define GPI_INT_STS_0 0x300 +#define GPI_INT_EN_0 0x310 +#define GPI_GPE_STS_0 0x330 +#define GPI_GPE_EN_0 0x350 +#define GPI_SMI_STS_0 0x370 +#define GPI_SMI_EN_0 0x390 +#define GPI_NMI_STS_0 0x3b0 +#define GPI_NMI_EN_0 0x3d0 +#define PAD_CFG_BASE 0x800 +#define GPP_V_START_OFFSET 0x800 +#define GPP_C_START_OFFSET 0x980 +#define GPP_F_START_OFFSET 0x800 +/* + * NOTE: GPP_E00 is not a connected PAD in PTL. However, for GPIO ASL file, the + * GPP_E00 offset 0x9a0 should be used for GPP_E group as the starting address + * and the total number of GPP_E group PAD is 25, E00-E22 + two internal only + * PADs at the end as defined in SOC gpio_soc_defs.h. GPP_E00 should be treated + * it as other internal used only PADs and does not meant to be used. + * ref doc: Panther Lake H GPIO Implementation Summary (#817954) + */ +#define GPP_E_START_OFFSET 0x9a0 +#define GPP_CPUJTAG_START_OFFSET 0x800 +#define GPP_H_START_OFFSET 0x8f0 +#define GPP_A_START_OFFSET 0xab0 +#define GPP_VGPIO3_START_OFFSET 0xc70 +#define GPP_S_START_OFFSET 0x800 +#define GPP_B_START_OFFSET 0x800 +#define GPP_D_START_OFFSET 0x9b0 +#define GPP_VGPIO_START_OFFSET 0xb60 + +#endif //_SOC_PANTHERLAKE_GPIO_DEFS_H_ diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..0937d1e --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,572 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ + +#define INC(x) ((x) + 1) + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +/* GPIO COMM 0 */ +#define GPP_V 0x0 +#define GPP_C 0x1 +/* GPIO COMM 1 */ +#define GPP_F 0x2 +#define GPP_E 0x3 +/* GPIO COMM 3 */ +#define GPP_A 0x4 +#define GPP_H 0x5 +/* GPIO COMM 4 */ +#define GPP_S 0x9 +/* GPIO COMM 5 */ +#define GPP_B 0x7 +#define GPP_D 0x8 +#define GPP_VGPIO 0x6 + +/* for ACPI _UID */ +#define GPP_COMM0_ID 0 +#define GPP_COMM1_ID 1 +#define GPP_COMM3_ID 3 +#define GPP_COMM4_ID 4 +#define GPP_COMM5_ID 5 + +#define GPP_V_NAME "GPP_V" +#define GPP_C_NAME "GPP_C" +#define GPP_F_NAME "GPP_F" +#define GPP_E_NAME "GPP_E" +#define GPP_CPUJTAG_NAME "GPUJTAG" +#define GPP_H_NAME "GPP_H" +#define GPP_A_NAME "GPP_A" +#define GPP_VGPIO3_NAME "vGPIO_3" +#define GPP_S_NAME "GPP_S" +#define GPP_B_NAME "GPP_B" +#define GPP_D_NAME "GPP_D" +#define GPP_VGPIO_NAME "vGPIO" + +#define GPIO_MAX_NUM_PER_GROUP 28 + +#define COMM_0 0 +#define COMM_1 INC(COMM_0) +#define COMM_3 INC(COMM_1) +#define COMM_4 INC(COMM_3) +#define COMM_5 INC(COMM_4) + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* + * +----------------------------+ + * | Community 0 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group V | + * +------------------+---------+ + * | | PTL-U/H | + * +------------------+---------+ + * | Pad Start Number | 0 | + * +------------------+---------+ + * | Pad End Number | 23 | + * +------------------+---------+ + */ +#define GPP_V00 0 +#define GPP_V01 INC(GPP_V00) +#define GPP_V02 INC(GPP_V01) +#define GPP_V03 INC(GPP_V02) +#define GPP_V04 INC(GPP_V03) +#define GPP_V05 INC(GPP_V04) +#define GPP_V06 INC(GPP_V05) +#define GPP_V07 INC(GPP_V06) +#define GPP_V08 INC(GPP_V07) +#define GPP_V09 INC(GPP_V08) +#define GPP_V10 INC(GPP_V09) +#define GPP_V11 INC(GPP_V10) +#define GPP_V12 INC(GPP_V11) +#define GPP_V13 INC(GPP_V12) +#define GPP_V14 INC(GPP_V13) +#define GPP_V15 INC(GPP_V14) +#define GPP_V16 INC(GPP_V15) +#define GPP_V17 INC(GPP_V16) + +#define GPP_PWROK INC(GPP_V17) +#define GPP_RESET_B INC(GPP_PWROK) +#define GPP_BKLTEN INC(GPP_RESET_B) +#define GPP_BKLTCTL INC(GPP_BKLTEN) +#define GPP_VDDEN INC(GPP_BKLTCTL) +#define GPP_RST_B INC(GPP_VDDEN) + +#define NUM_GRP_V_PADS (GPP_RST_B - GPP_V00 + 1) +#define NUM_GPP_V_PADS (GPP_V17 - GPP_V00 + 1) + +/* + * +----------------------------+ + * | Group C | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 24 | + * +------------------+---------+ + * | Pad End Number | 47 | + * +------------------+---------+ + */ +#define GPP_C00 INC(GPP_RST_B) +#define GPP_C01 INC(GPP_C00) +#define GPP_C02 INC(GPP_C01) +#define GPP_C03 INC(GPP_C02) +#define GPP_C04 INC(GPP_C03) +#define GPP_C05 INC(GPP_C04) +#define GPP_C06 INC(GPP_C05) +#define GPP_C07 INC(GPP_C06) +#define GPP_C08 INC(GPP_C07) +#define GPP_C09 INC(GPP_C08) +#define GPP_C10 INC(GPP_C09) +#define GPP_C11 INC(GPP_C10) +#define GPP_C12 INC(GPP_C11) +#define GPP_C13 INC(GPP_C12) +#define GPP_C14 INC(GPP_C13) +#define GPP_C15 INC(GPP_C14) +#define GPP_C16 INC(GPP_C15) +#define GPP_C17 INC(GPP_C16) +#define GPP_C18 INC(GPP_C17) +#define GPP_C19 INC(GPP_C18) +#define GPP_C20 INC(GPP_C19) +#define GPP_C21 INC(GPP_C20) +#define GPP_C22 INC(GPP_C21) +#define GPP_C23 INC(GPP_C22) + +#define NUM_GRP_C_PADS (GPP_C23 - GPP_C00 + 1) +#define NUM_GPP_C_PADS (GPP_C23 - GPP_C00 + 1) + +#define COM0_GRP_PAD_START GPP_V00 +#define COM0_GRP_PAD_END GPP_C23 +#define NUM_COM0_GRP_PADS (GPP_C23 - GPP_V00 + 1) +#define NUM_COM0_GPP_PADS (NUM_GPP_V_PADS + NUM_GPP_C_PADS) +#define NUM_COM0_GROUPS 2 + +/* + * +----------------------------+ + * | Community 1 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group F | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 48 | + * +------------------+---------+ + * | Pad End Number | 73 | + * +------------------+---------+ + */ +#define GPP_F00 INC(GPP_C23) +#define GPP_F01 INC(GPP_F00) +#define GPP_F02 INC(GPP_F01) +#define GPP_F03 INC(GPP_F02) +#define GPP_F04 INC(GPP_F03) +#define GPP_F05 INC(GPP_F04) +#define GPP_F06 INC(GPP_F05) +#define GPP_F07 INC(GPP_F06) +#define GPP_F08 INC(GPP_F07) +#define GPP_F09 INC(GPP_F08) +#define GPP_F10 INC(GPP_F09) +#define GPP_F11 INC(GPP_F10) +#define GPP_F12 INC(GPP_F11) +#define GPP_F13 INC(GPP_F12) +#define GPP_F14 INC(GPP_F13) +#define GPP_F15 INC(GPP_F14) +#define GPP_F16 INC(GPP_F15) +#define GPP_F17 INC(GPP_F16) +#define GPP_F18 INC(GPP_F17) +#define GPP_F19 INC(GPP_F18) +#define GPP_F20 INC(GPP_F19) +#define GPP_F21 INC(GPP_F20) +#define GPP_F22 INC(GPP_F21) +#define GPP_F23 INC(GPP_F22) +#define GPP_THC1_GSPI1_CLK_LPBK INC(GPP_F23) +#define GPP_GSPI0_CLK_LOOPBK INC(GPP_THC1_GSPI1_CLK_LPBK) + +#define NUM_GRP_F_PADS (GPP_GSPI0_CLK_LOOPBK - GPP_F00 + 1) +#define NUM_GPP_F_PADS (GPP_F23 - GPP_F00 + 1) + +/* + * +----------------------------+ + * | Group E | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 74 | + * +------------------+---------+ + * | Pad End Number | 98 | + * +------------------+---------+ + * + * NOTE: GPP_E00 is not a connected PAD in PTL and should be treated + * as other internal used only PADs. It does not meant to be used. + * ref doc: Panther Lake H GPIO Implementation Summary (#817954) + */ +#define GPP_E00 INC(GPP_GSPI0_CLK_LOOPBK) +#define GPP_E01 INC(GPP_E00) +#define GPP_E02 INC(GPP_E01) +#define GPP_E03 INC(GPP_E02) +#define GPP_E04 INC(GPP_E03) +#define GPP_E05 INC(GPP_E04) +#define GPP_E06 INC(GPP_E05) +#define GPP_E07 INC(GPP_E06) +#define GPP_E08 INC(GPP_E07) +#define GPP_E09 INC(GPP_E08) +#define GPP_E10 INC(GPP_E09) +#define GPP_E11 INC(GPP_E10) +#define GPP_E12 INC(GPP_E11) +#define GPP_E13 INC(GPP_E12) +#define GPP_E14 INC(GPP_E13) +#define GPP_E15 INC(GPP_E14) +#define GPP_E16 INC(GPP_E15) +#define GPP_E17 INC(GPP_E16) +#define GPP_E18 INC(GPP_E17) +#define GPP_E19 INC(GPP_E18) +#define GPP_E20 INC(GPP_E19) +#define GPP_E21 INC(GPP_E20) +#define GPP_E22 INC(GPP_E21) +#define GPP_BOOTHALT_B INC(GPP_E22) +#define GPP_THC0_GSPI_CLK_LPBK INC(GPP_BOOTHALT_B) + +#define NUM_GRP_E_PADS (GPP_THC0_GSPI_CLK_LPBK - GPP_E00 + 1) +#define NUM_GPP_E_PADS (GPP_E22 - GPP_E00 + 1) + +#define COM1_GRP_PAD_START GPP_F00 +#define COM1_GRP_PAD_END GPP_THC0_GSPI_CLK_LPBK +#define NUM_COM1_GRP_PADS (GPP_THC0_GSPI_CLK_LPBK - GPP_F00 + 1) +#define NUM_COM1_GPP_PADS (NUM_GPP_F_PADS + NUM_GPP_E_PADS) +#define NUM_COM1_GROUPS 2 + +/* + * +----------------------------+ + * | Community 3 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group CPUJTAG | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 99 | + * +------------------+---------+ + * | Pad End Number | 113 | + * +------------------+---------+ + */ + +#define GPP_EPD_ON INC(GPP_THC0_GSPI_CLK_LPBK) +#define GPP_VDD2_PWRGD INC(GPP_EPD_ON) + +#define GPP_JTAG_MBPB0 INC(GPP_VDD2_PWRGD) +#define GPP_JTAG_MBPB1 INC(GPP_JTAG_MBPB0) +#define GPP_JTAG_MBPB2 INC(GPP_JTAG_MBPB1) +#define GPP_JTAG_MBPB3 INC(GPP_JTAG_MBPB2) +#define GPP_JTAG_TD0 INC(GPP_JTAG_MBPB3) +#define GPP_PRDY_B INC(GPP_JTAG_TD0) +#define GPP_PREQ_B INC(GPP_PRDY_B) +#define GPP_JTAG_TDI INC(GPP_PREQ_B) +#define GPP_JTAG_TMS INC(GPP_JTAG_TDI) +#define GPP_JTAG_TCK INC(GPP_JTAG_TMS) +#define GPP_DBG_PMODE INC(GPP_JTAG_TCK) +#define GPP_JTAG_TRST_B INC(GPP_DBG_PMODE) +#define GPP_DDSP_HPDALV INC(GPP_JTAG_TRST_B) + +#define NUM_GRP_CPUJTAG_PADS (GPP_DDSP_HPDALV - GPP_EPD_ON + 1) + +/* + * +----------------------------+ + * | Group H | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 114 | + * +------------------+---------+ + * | Pad End Number | 141 | + * +------------------+---------+ + */ +#define GPP_H00 INC(GPP_DDSP_HPDALV) +#define GPP_H01 INC(GPP_H00) +#define GPP_H02 INC(GPP_H01) +#define GPP_H03 INC(GPP_H02) +#define GPP_H04 INC(GPP_H03) +#define GPP_H05 INC(GPP_H04) +#define GPP_H06 INC(GPP_H05) +#define GPP_H07 INC(GPP_H06) +#define GPP_H08 INC(GPP_H07) +#define GPP_H09 INC(GPP_H08) +#define GPP_H10 INC(GPP_H09) +#define GPP_H11 INC(GPP_H10) +#define GPP_H12 INC(GPP_H11) +#define GPP_H13 INC(GPP_H12) +#define GPP_H14 INC(GPP_H13) +#define GPP_H15 INC(GPP_H14) +#define GPP_H16 INC(GPP_H15) +#define GPP_H17 INC(GPP_H16) +#define GPP_H18 INC(GPP_H17) +#define GPP_H19 INC(GPP_H18) +#define GPP_H20 INC(GPP_H19) +#define GPP_H21 INC(GPP_H20) +#define GPP_H22 INC(GPP_H21) +#define GPP_H23 INC(GPP_H22) +#define GPP_H24 INC(GPP_H23) +#define GPP_LPI3C1_CLK_LPBK INC(GPP_H24) +#define GPP_LPI3C0_CLK_LPBK INC(GPP_LPI3C1_CLK_LPBK) +#define GPP_ISHI3C1_CLK_LPBK INC(GPP_LPI3C0_CLK_LPBK) + +#define NUM_GRP_H_PADS (GPP_ISHI3C1_CLK_LPBK - GPP_H00 + 1) +#define NUM_GPP_H_PADS (GPP_H24 - GPP_H00 + 1) + +/* + * +----------------------------+ + * | Group A | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 142 | + * +------------------+---------+ + * | Pad End Number | 169 | + * +------------------+---------+ + */ +#define GPP_A00 INC(GPP_ISHI3C1_CLK_LPBK) +#define GPP_A01 INC(GPP_A00) +#define GPP_A02 INC(GPP_A01) +#define GPP_A03 INC(GPP_A02) +#define GPP_A04 INC(GPP_A03) +#define GPP_A05 INC(GPP_A04) +#define GPP_A06 INC(GPP_A05) +#define GPP_A07 INC(GPP_A06) +#define GPP_A08 INC(GPP_A07) +#define GPP_A09 INC(GPP_A08) +#define GPP_A10 INC(GPP_A09) +#define GPP_A11 INC(GPP_A10) +#define GPP_A12 INC(GPP_A11) +#define GPP_A13 INC(GPP_A12) +#define GPP_A14 INC(GPP_A13) +#define GPP_A15 INC(GPP_A14) +#define GPP_A16 INC(GPP_A15) +#define GPP_A17 INC(GPP_A16) +/* SPI0 PADs */ +#define GPP_SPI0_IO_2 INC(GPP_A17) +#define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2) +#define GPP_SPI0_MOSI_IO_0 INC(GPP_SPI0_IO_3) +#define GPP_SPI0_MOSI_IO_1 INC(GPP_SPI0_MOSI_IO_0) +#define GPP_SPI0_TPM_CS_B INC(GPP_SPI0_MOSI_IO_1) +#define GPP_SPI0_FLASH_0_CS_B INC(GPP_SPI0_TPM_CS_B) +#define GPP_SPI0_FLASH_1_CS_B INC(GPP_SPI0_FLASH_0_CS_B) +#define GPP_SPI0_CLK INC(GPP_SPI0_FLASH_1_CS_B) +#define GPP_ESPI_CLK_LPBK INC(GPP_SPI0_CLK) +#define GPP_SPI0_CLK_LOOPBK INC(GPP_ESPI_CLK_LPBK) + +#define NUM_GRP_A_PADS (GPP_SPI0_CLK_LOOPBK - GPP_A00 + 1) +#define NUM_GPP_A_PADS (GPP_A17 - GPP_A00 + 1) + +/* + * +----------------------------+ + * | Group vGPIO3 | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 170 | + * +------------------+---------+ + * | Pad End Number | 183 | + * +------------------+---------+ + */ +#define GPP_VGPIO3_USB0 INC(GPP_SPI0_CLK_LOOPBK) +#define GPP_VGPIO3_USB1 INC(GPP_VGPIO3_USB0) +#define GPP_VGPIO3_USB2 INC(GPP_VGPIO3_USB1) +#define GPP_VGPIO3_USB3 INC(GPP_VGPIO3_USB2) +#define GPP_VGPIO3_USB4 INC(GPP_VGPIO3_USB3) +#define GPP_VGPIO3_USB5 INC(GPP_VGPIO3_USB4) +#define GPP_VGPIO3_USB6 INC(GPP_VGPIO3_USB5) +#define GPP_VGPIO3_USB7 INC(GPP_VGPIO3_USB6) +#define GPP_VGPIO3_TS0 INC(GPP_VGPIO3_USB7) +#define GPP_VGPIO3_TS1 INC(GPP_VGPIO3_TS0) +#define GPP_VGPIO3_THC0 INC(GPP_VGPIO3_TS1) +#define GPP_VGPIO3_THC1 INC(GPP_VGPIO3_THC0) +#define GPP_VGPIO3_THC2 INC(GPP_VGPIO3_THC1) +#define GPP_VGPIO3_THC3 INC(GPP_VGPIO3_THC2) + +#define NUM_GRP_VGPIO3_PADS (GPP_VGPIO3_THC3 - GPP_VGPIO3_USB0 + 1) + +#define COM3_GRP_PAD_START GPP_EPD_ON +#define COM3_GRP_PAD_END GPP_VGPIO3_THC3 +#define NUM_COM3_GRP_PADS (GPP_VGPIO3_THC3 - GPP_EPD_ON + 1) +#define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) +#define NUM_COM3_GROUPS 4 + +/* + * +----------------------------+ + * | Community 4 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group S | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 184 | + * +------------------+---------+ + * | Pad End Number | 191 | + * +------------------+---------+ + */ +#define GPP_S00 INC(GPP_VGPIO3_THC3) +#define GPP_S01 INC(GPP_S00) +#define GPP_S02 INC(GPP_S01) +#define GPP_S03 INC(GPP_S02) +#define GPP_S04 INC(GPP_S03) +#define GPP_S05 INC(GPP_S04) +#define GPP_S06 INC(GPP_S05) +#define GPP_S07 INC(GPP_S06) + +#define NUM_GRP_S_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_GPP_S_PADS (GPP_S07 - GPP_S00 + 1) + +#define COM4_GRP_PAD_START GPP_S00 +#define COM4_GRP_PAD_END GPP_S07 +#define NUM_COM4_GRP_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_COM4_GPP_PADS (GPP_S07 - GPP_S00 + 1) +#define NUM_COM4_GROUPS 1 + +/* + * +----------------------------+ + * | Community 5 | + * +----------------------------+ + */ + +/* + * +----------------------------+ + * | Group B | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 192 | + * +------------------+---------+ + * | Pad End Number | 218 | + * +------------------+---------+ + */ +#define GPP_B00 INC(GPP_S07) +#define GPP_B01 INC(GPP_B00) +#define GPP_B02 INC(GPP_B01) +#define GPP_B03 INC(GPP_B02) +#define GPP_B04 INC(GPP_B03) +#define GPP_B05 INC(GPP_B04) +#define GPP_B06 INC(GPP_B05) +#define GPP_B07 INC(GPP_B06) +#define GPP_B08 INC(GPP_B07) +#define GPP_B09 INC(GPP_B08) +#define GPP_B10 INC(GPP_B09) +#define GPP_B11 INC(GPP_B10) +#define GPP_B12 INC(GPP_B11) +#define GPP_B13 INC(GPP_B12) +#define GPP_B14 INC(GPP_B13) +#define GPP_B15 INC(GPP_B14) +#define GPP_B16 INC(GPP_B15) +#define GPP_B17 INC(GPP_B16) +#define GPP_B18 INC(GPP_B17) +#define GPP_B19 INC(GPP_B18) +#define GPP_B20 INC(GPP_B19) +#define GPP_B21 INC(GPP_B20) +#define GPP_B22 INC(GPP_B21) +#define GPP_B23 INC(GPP_B22) +#define GPP_B24 INC(GPP_B23) +#define GPP_B25 INC(GPP_B24) +#define GPP_ISHI3C0_CLK_LPBK INC(GPP_B25) + +#define NUM_GRP_B_PADS (GPP_ISHI3C0_CLK_LPBK - GPP_B00 + 1) +#define NUM_GPP_B_PADS (GPP_B25 - GPP_B00 + 1) + +/* + * +----------------------------+ + * | Group D | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 219 | + * +------------------+---------+ + * | Pad End Number | 245 | + * +------------------+---------+ + */ +#define GPP_D00 INC(GPP_ISHI3C0_CLK_LPBK) +#define GPP_D01 INC(GPP_D00) +#define GPP_D02 INC(GPP_D01) +#define GPP_D03 INC(GPP_D02) +#define GPP_D04 INC(GPP_D03) +#define GPP_D05 INC(GPP_D04) +#define GPP_D06 INC(GPP_D05) +#define GPP_D07 INC(GPP_D06) +#define GPP_D08 INC(GPP_D07) +#define GPP_D09 INC(GPP_D08) +#define GPP_D10 INC(GPP_D09) +#define GPP_D11 INC(GPP_D10) +#define GPP_D12 INC(GPP_D11) +#define GPP_D13 INC(GPP_D12) +#define GPP_D14 INC(GPP_D13) +#define GPP_D15 INC(GPP_D14) +#define GPP_D16 INC(GPP_D15) +#define GPP_D17 INC(GPP_D16) +#define GPP_D18 INC(GPP_D17) +#define GPP_D19 INC(GPP_D18) +#define GPP_D20 INC(GPP_D19) +#define GPP_D21 INC(GPP_D20) +#define GPP_D22 INC(GPP_D21) +#define GPP_D23 INC(GPP_D22) +#define GPP_D24 INC(GPP_D23) +#define GPP_D25 INC(GPP_D24) +#define GPP_ISDI3C1_CLK_LPBK INC(GPP_D25) + +#define NUM_GRP_D_PADS (GPP_ISDI3C1_CLK_LPBK - GPP_D00 + 1) +#define NUM_GPP_D_PADS (GPP_D25 - GPP_D00 + 1) + +/* + * +----------------------------+ + * | Group vGPIO | + * +------------------+---------+ + * | | PTL-UH/H| + * +------------------+---------+ + * | Pad Start Number | 246 | + * +------------------+---------+ + * | Pad End Number | 263 | + * +------------------+---------+ + */ +#define GPP_VGPIO0 INC(GPP_ISDI3C1_CLK_LPBK) +#define GPP_VGPIO5 INC(GPP_VGPIO0) +#define GPP_VGPIO30 INC(GPP_VGPIO5) +#define GPP_VGPIO31 INC(GPP_VGPIO30) +#define GPP_VGPIO32 INC(GPP_VGPIO31) +#define GPP_VGPIO33 INC(GPP_VGPIO32) +#define GPP_VGPIO34 INC(GPP_VGPIO33) +#define GPP_VGPIO35 INC(GPP_VGPIO34) +#define GPP_VGPIO36 INC(GPP_VGPIO35) +#define GPP_VGPIO37 INC(GPP_VGPIO36) +#define GPP_VGPIO40 INC(GPP_VGPIO37) +#define GPP_VGPIO41 INC(GPP_VGPIO40) +#define GPP_VGPIO42 INC(GPP_VGPIO41) +#define GPP_VGPIO43 INC(GPP_VGPIO42) +#define GPP_VGPIO44 INC(GPP_VGPIO43) +#define GPP_VGPIO45 INC(GPP_VGPIO44) +#define GPP_VGPIO46 INC(GPP_VGPIO45) +#define GPP_VGPIO47 INC(GPP_VGPIO46) + +#define NUM_GRP_VGPIO_PADS (GPP_VGPIO47 - GPP_VGPIO0 + 1) + +#define COM5_GRP_PAD_START GPP_B00 +#define COM5_GRP_PAD_END GPP_VGPIO47 +#define NUM_COM5_GRP_PADS (GPP_VGPIO47 - GPP_B00 + 1) +#define NUM_COM5_GPP_PADS (NUM_GPP_B_PADS + NUM_GPP_D_PADS) +#define NUM_COM5_GROUPS 3 + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (COM5_GRP_PAD_END + 1) + +#endif /* _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 72 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>

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[XS] Change in coreboot[main]: Doc/rmodules.md: Move to lib
by Nicholas Chin (Code Review) 07 Sep '24

07 Sep '24

Attention is currently required from: Nico Huber. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84240?usp=email ) Change subject: Doc/rmodules.md: Move to lib ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I'd rather not. This seems to become a sinkhole for coreboot guides and concepts […] Ack, moved it to lib instead. I agree that the TOC is a bit of a mess and that things could be reorganized. I had previously been thinking of making a debugging section somewhere to document how to use/find/etc various methods of debugging, and that console page could be moved there (and probably factored out/renamed to an SMBus console specific page and an index.md with all the pages) -- To view, visit https://review.coreboot.org/c/coreboot/+/84240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Gerrit-Change-Number: 84240 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 07 Sep 2024 18:32:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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