coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro
by Felix Singer (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84099?usp=email ) Change subject: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Gerrit-Change-Number: 84099 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 21:46:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Docs: Revert false MyST Parser toctree conversions
by Felix Singer (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth, Nicholas Chin. Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84244?usp=email ) Change subject: Docs: Revert false MyST Parser toctree conversions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Gerrit-Change-Number: 84244 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 21:45:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 21: (20 comments) File src/soc/intel/snowridge/Kconfig: https://review.coreboot.org/c/coreboot/+/83321/comment/1fb1a946_d134e082?us… : PS15, Line 123: default 0x3ff00 if FSP_CAR > Are FSP_CAR and !FSP_CAR both validated? Only FSP_CAR is valid, I will remove the untested one. https://review.coreboot.org/c/coreboot/+/83321/comment/9b3d841b_c74d1ebe?us… : PS15, Line 244: 0xfe00000. It will be used until coreboot resource allocation overwrite it > 0xfe000000? Done File src/soc/intel/snowridge/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83321/comment/d98d4dbb_0d8fdeac?us… : PS15, Line 60: endif ## CONFIG_SOC_INTEL_FSP_SNOWRIDGE > CONFIG_SOC_INTEL_SNOWRIDGE Done File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/198d78c2_5c0d20b8?us… : PS15, Line 243: if (read32p(HPET_BASE_ADDRESS + 0x100) & 0x00008000) { > are there macros for these constants? The same code also exists in src/soc/intel/xeon_sp/uncore_acpi.c. I will add a separate patch that adds macros and update that file. File src/soc/intel/snowridge/acpi/ith.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/8368517d_1a1c209d?us… : PS17, Line 2: > if this is not referred, clean it? maybe to clean to a minimal asl set? It's referred by the last line of southcluster.asl. File src/soc/intel/snowridge/bootblock/early_uart_init.c: https://review.coreboot.org/c/coreboot/+/83321/comment/848f1c28_876faf51?us… : PS15, Line 11: static void pci_early_hsuart_device_probe(uint8_t bus, uint8_t dev, uint8_t func, > probe -> enable? Done https://review.coreboot.org/c/coreboot/+/83321/comment/31a08eb7_a8c7e117?us… : PS15, Line 43: write32p(reg32 + UCMR_OFFSET, read32p(reg32 + UCMR_OFFSET) * HIGH_SPEED_CLK_MULT); > reg32 -> iobase? Done File src/soc/intel/snowridge/chip.h: https://review.coreboot.org/c/coreboot/+/83321/comment/406c01f9_6eee1984?us… : PS15, Line 12: * additional root bus in stack 2 and 7 (UBox1). > So what is for stack 2? It's Intel Dynamic Load Balancer, I will update the comments. File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/3dc3ed6a_58885d73?us… : PS15, Line 75: if (sr[i].Personality >= BL_TYPE_DISABLED) > is there any reason not using !=? For SNR, each type of stack has its own disabled enumeration value, see BL_STACK_TYPE in src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h. I will also update the comment. https://review.coreboot.org/c/coreboot/+/83321/comment/c04c22cc_69a20b15?us… : PS15, Line 180: int i; > for (int i = 0; ... […] Done File src/soc/intel/snowridge/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83321/comment/707fbecb_e6af8552?us… : PS15, Line 22: #define GPIO_WEST2_PADCFGLOCKTX 0x00c4 > Not sure if these cfg registers are the same across community/groups? If yes, if it is possible to o […] These sets of values are used to define struct pad_community, see src/soc/intel/snowridge/common/gpio.c. File src/soc/intel/snowridge/lockdown.c: https://review.coreboot.org/c/coreboot/+/83321/comment/65eae10a_96235654?us… : PS15, Line 22: if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) > is CHIPSET_LOCKDOWN_FSP be tested? If no, we could just assert only support coreboot lockdown? It's not tested, replacing it with an assert is more reasonable. File src/soc/intel/snowridge/romstage/gpio_snr.c: https://review.coreboot.org/c/coreboot/+/83321/comment/becd718b_18340ea5?us… : PS15, Line 145: for (j = i + 1; j < num; j++) { > this assumes the bits in the same group are placed together, if removing this assumption, will this […] It still works. Since configuration lock registers for pads in the same group are in the same 32-bit registers, the inner for-j loop will collect and unlock them in one PCR sideband message. I will remove the inner loop if there is no significant impacts on the performance. https://review.coreboot.org/c/coreboot/+/83321/comment/649b97fc_907b0d91?us… : PS15, Line 160: */ > so the assumption is: only pad_config_mask covered bits are with explicit setting, while the not cov […] yes. https://review.coreboot.org/c/coreboot/+/83321/comment/ca8e436c_d53ec631?us… : PS15, Line 207: if (comm_index != SNR_GPIO_COMMUNITY(gpio[j].cfg.pad) || > if remove this assumption, there will be duplicated settings, but the result will be still correct. […] I think we can just remove the inner for-j loop just for simplicity. File src/soc/intel/snowridge/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/83321/comment/4c600f62_ce527c30?us… : PS15, Line 133: channel < ARRAY_SIZE(fsp_smbios_memory_info->ChannelInfo) && > assume fsp_smbios_memory_info->ChannelCount == ARRAY_SIZE(fsp_smbios_memory_info->ChannelInfo)? From FSP outputs, it seems ChannelCount is equal to array size of ChannelInfo. I think I can add an assert to simplify the for condition. https://review.coreboot.org/c/coreboot/+/83321/comment/620659ae_2e990335?us… : PS15, Line 139: dimm < ARRAY_SIZE(channel_info->DimmInfo) && > assume dimm < channel_info->DimmCoun == dimm < ARRAY_SIZE(channel_info->DimmInfo)? I will add an assert for DimmCount and DimmInfo. File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/87abb042_ab5447df?us… : PS15, Line 32: void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt) > resource_cnt -> resource_index? The parameter in the declaration is resource_cnt, but all the SoC implementations renamed it to index. Maybe we need another patch to keep them consistent. https://review.coreboot.org/c/coreboot/+/83321/comment/d3d18c4c_8b6b5d13?us… : PS15, Line 33: { > The resource_cnt is a bit confusing, is there cases where resource_cnt != 1? This pointer is passed from common system agent code, representing current assigned resources in system agent, then passed to sa_add_fixed_mmio_resources. When it returns, it will be increased. https://review.coreboot.org/c/coreboot/+/83321/comment/2d0c9ca1_42d352d9?us… : PS15, Line 56: I > PCIe MMCFG BAR? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 21 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 08 Sep 2024 13:29:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: ec/hp/kbc1126/acpi: Clean up GBSS
by Nicholas Sudsgaard (Code Review) 08 Sep '24

08 Sep '24

Nicholas Sudsgaard has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/84247?usp=email ) Change subject: ec/hp/kbc1126/acpi: Clean up GBSS ...................................................................... ec/hp/kbc1126/acpi: Clean up GBSS This changes the format of the serial number slightly, as it does not add any zero padding. Old format: %05d %04d/%02d/%02d New format: %d %d/%d/%d TEST=Produces correct serial number on HP ProBook 450 G3 Change-Id: I12066526dc0031513488884f38c5bd4130206761 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/ec/hp/kbc1126/acpi/battery.asl 1 file changed, 11 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84247/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12066526dc0031513488884f38c5bd4130206761 Gerrit-Change-Number: 84247 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[S] Change in coreboot[main]: ec/hp/kbc1126/acpi: Clean up GBSS
by Nicholas Sudsgaard (Code Review) 08 Sep '24

08 Sep '24

Nicholas Sudsgaard has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84247?usp=email ) Change subject: ec/hp/kbc1126/acpi: Clean up GBSS ...................................................................... ec/hp/kbc1126/acpi: Clean up GBSS This changes the format of the serial number slightly, as it does not add any zero padding. Old format: %05d %04d/%02d/%02d New format: %d %d/%d/%d TEST=Produces correct serial number on HP ProBook 450 G3 Change-Id: I12066526dc0031513488884f38c5bd4130206761 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/ec/hp/kbc1126/acpi/battery.asl 1 file changed, 7 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84247/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12066526dc0031513488884f38c5bd4130206761 Gerrit-Change-Number: 84247 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[S] Change in coreboot[main]: ec/hp/kbc1126/acpi: Clean up GBSS
by Nicholas Sudsgaard (Code Review) 08 Sep '24

08 Sep '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84247?usp=email ) Change subject: ec/hp/kbc1126/acpi: Clean up GBSS ...................................................................... ec/hp/kbc1126/acpi: Clean up GBSS This changes the format of the serial number slightly, as it does not add any zero padding. Old format: %05d %04d/%02d/%02d New format: %d %d/%d/%d TEST=Produces correct serial number on HP ProBook 450 G3 Change-Id: I12066526dc0031513488884f38c5bd4130206761 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/ec/hp/kbc1126/acpi/battery.asl 1 file changed, 8 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84247/1 diff --git a/src/ec/hp/kbc1126/acpi/battery.asl b/src/ec/hp/kbc1126/acpi/battery.asl index b1e9f2d..3acb0e5 100644 --- a/src/ec/hp/kbc1126/acpi/battery.asl +++ b/src/ec/hp/kbc1126/acpi/battery.asl @@ -196,40 +196,16 @@ 0x04B0 }) -Method (\ISTR, 2, Serialized) -{ - Name (NUMB, Buffer (6) { " " }) - Local0 = Arg0 - Local1 = Arg1 - While (Local1) - { - Local1-- - Local2 = Local0 % 10 - Local0 = Local0 / 10 - NUMB[Local1] = Local2 + 48 - } - ToString (NUMB, Arg1, Local3) - Return (Local3) -} - Method (GBSS, 2, Serialized) { - Local3 = \ISTR (Arg0, 0x05) - Concatenate (Local3, " ", Local4) - Local0 = (Arg1 >> 0x09) - Local1 = (Local0 + 1980) - Local2 = \ISTR (Local1, 0x04) - Concatenate (Local4, Local2, Local3) - Concatenate (Local3, "/", Local4) - Local0 = (Arg1 >> 0x05) - Local1 = (Local0 & 0x0F) - Local2 = \ISTR (Local1, 0x02) - Concatenate (Local4, Local2, Local3) - Concatenate (Local3, "/", Local4) - Local1 = (Arg1 & 0x1F) - Local2 = \ISTR (Local1, 0x02) - Concatenate (Local4, Local2, Local3) - Return (Local3) + Local0 = "" + Fprintf(Local0, "%o %o/%o/%o", + ToDecimalString(Arg0), + ToDecimalString(((Arg1 >> 9) & 0x7F) + 1980), + ToDecimalString((Arg1 >> 5) & 0x0F), + ToDecimalString((Arg1 >> 0) & 0x1F) + ) + Return (Local0) } Method (BTIG, 1, Serialized) /* in vendor DSDT is EC0.BTIF */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12066526dc0031513488884f38c5bd4130206761 Gerrit-Change-Number: 84247 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[XL] Change in coreboot[main]: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro
by Nicholas Sudsgaard (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Nicholas Chin. Nicholas Sudsgaard has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84099?usp=email ) Change subject: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Gerrit-Change-Number: 84099 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 11:43:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro
by Elyes Haouas (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Nicholas Chin. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84099?usp=email ) Change subject: mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macro ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Gerrit-Change-Number: 84099 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Sep 2024 09:51:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/getac/p470/hda_verb: Use macros instead of magic numbers
by Elyes Haouas (Code Review) 08 Sep '24

08 Sep '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84246?usp=email ) Change subject: mb/getac/p470/hda_verb: Use macros instead of magic numbers ...................................................................... mb/getac/p470/hda_verb: Use macros instead of magic numbers Change-Id: I247ac1ae88a623489a98e876ea10d8515b6f3e9d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/hda_verb.c 1 file changed, 108 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/84246/1 diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c index e7e5828..77db6a1 100644 --- a/src/mainboard/getac/p470/hda_verb.c +++ b/src/mainboard/getac/p470/hda_verb.c @@ -14,40 +14,136 @@ /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12), DMIC */ - AZALIA_PIN_CFG(0, 0x12, 0x411111F0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), /* Pin Complex (NID 0x14), LINE_OUT (port D) */ - AZALIA_PIN_CFG(0, 0x14, 0x99130110), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 16 + )), /* Pin Complex (NID 0x15), HP_OUT (port A) */ - AZALIA_PIN_CFG(0, 0x15, 0x01214020), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 32 + )), /* Pin Complex (NID 0x16), MONO-OUT */ - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), /* Pin Complex (NID 0x18), MIC1 (port B) */ - AZALIA_PIN_CFG(0, 0x18, 0x01A19830), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 48 + )), /* Pin Complex (NID 0x19), MIC2 (port F) */ - AZALIA_PIN_CFG(0, 0x19, 0x99A30931), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 2, 0 + )), /* Pin Complex (NID 0x1A), LINE1 (port C) */ - AZALIA_PIN_CFG(0, 0x1A, 0x02A1983F), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + AZALIA_JACK_PRESENCE_DETECT, + 1, 63 + )), /* Pin Complex (NID 0x1B), LINE2 (port E) */ - AZALIA_PIN_CFG(0, 0x1B, 0x0221401F), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 31 + )), /* Pin Complex (NID 0x1C), CD_IN */ - AZALIA_PIN_CFG(0, 0x1C, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1C, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_INTERNAL, + AZALIA_CD_IN, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), /* Pin Complex (NID 0x1D), PCBEEP */ - AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_BEEP, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), /* Pin Complex (NID 0x1E), S/PDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, + AZALIA_DIGITAL_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), /* Pin Complex (NID 0x1F), S/PDIF-IN */ - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_DIGITAL_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), }; const u32 pc_beep_verbs[0] = {}; -- To view, visit https://review.coreboot.org/c/coreboot/+/84246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I247ac1ae88a623489a98e876ea10d8515b6f3e9d Gerrit-Change-Number: 84246 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: Docs: Revert false MyST Parser toctree conversions
by Nicholas Chin (Code Review) 08 Sep '24

08 Sep '24

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Hello Angel Pons, Jason Glenesk, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84244?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Docs: Revert false MyST Parser toctree conversions ...................................................................... Docs: Revert false MyST Parser toctree conversions Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser) converted recommonmark style toctrees in bulk using a script. This was done by searching for lists of references, which is how recommonmark denoted toctree entries. However, this also converted lists of external URLs, which would not normally be included in the toctree. Revert these cases back to lists of URLs as they were before the migration. Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/kconfig.md M Documentation/infrastructure/builders.md M Documentation/mainboard/lenovo/ivb_internal_flashing.md M Documentation/mainboard/protectli/vp2420.md M Documentation/mainboard/protectli/vp46xx.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/index.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/technotes/console.md 15 files changed, 60 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84244/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Gerrit-Change-Number: 84244 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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