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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
Patch Set 22:
(8 comments)
File src/soc/intel/snowridge/Kconfig:
https://review.coreboot.org/c/coreboot/+/83321/comment/a9f3ab8b_6b46821e?us… :
PS15, Line 123: default 0x3ff00 if FSP_CAR
> Only FSP_CAR is valid, I will remove the untested one.
Done
File src/soc/intel/snowridge/acpi.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/5d5f2b0e_9249e6b2?us… :
PS15, Line 243: if (read32p(HPET_BASE_ADDRESS + 0x100) & 0x00008000) {
> The same code also exists in src/soc/intel/xeon_sp/uncore_acpi.c. […]
Patch link https://review.coreboot.org/c/coreboot/+/84252.
File src/soc/intel/snowridge/chip.h:
https://review.coreboot.org/c/coreboot/+/83321/comment/57893b82_d5f9056c?us… :
PS15, Line 12: * additional root bus in stack 2 and 7 (UBox1).
> It's Intel Dynamic Load Balancer, I will update the comments.
Done
File src/soc/intel/snowridge/chip.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/e93cce7e_5685652a?us… :
PS15, Line 75: if (sr[i].Personality >= BL_TYPE_DISABLED)
> For SNR, each type of stack has its own disabled enumeration value, see BL_STACK_TYPE in src/vendorc […]
Done
File src/soc/intel/snowridge/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/83321/comment/167a6181_9215a0b2?us… :
PS15, Line 22: #define GPIO_WEST2_PADCFGLOCKTX 0x00c4
> These sets of values are used to define struct pad_community, see src/soc/intel/snowridge/common/gpi […]
Done
File src/soc/intel/snowridge/lockdown.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/b792c53f_63886b45?us… :
PS15, Line 22: if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
> It's not tested, replacing it with an assert is more reasonable.
Done
File src/soc/intel/snowridge/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/c3f760c1_6ce3fd93?us… :
PS15, Line 133: channel < ARRAY_SIZE(fsp_smbios_memory_info->ChannelInfo) &&
> From FSP outputs, it seems ChannelCount is equal to array size of ChannelInfo. […]
Done
https://review.coreboot.org/c/coreboot/+/83321/comment/eecde6a5_459ee689?us… :
PS15, Line 139: dimm < ARRAY_SIZE(channel_info->DimmInfo) &&
> I will add an assert for DimmCount and DimmInfo.
Done
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Change subject: arch/x86: Define macros for hard-coded HPET registers
......................................................................
Patch Set 1: Code-Review+2
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Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83321?usp=email
to look at the new patch set (#22).
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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com>
---
M 3rdparty/fsp
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/systemagent_early.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_gpmr.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
74 files changed, 5,878 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/22
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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
Patch Set 21:
(5 comments)
File src/soc/intel/snowridge/acpi/ith.asl:
https://review.coreboot.org/c/coreboot/+/83321/comment/4dc282c7_113e665e?us… :
PS17, Line 2:
> It's referred by the last line of southcluster.asl.
Done
File src/soc/intel/snowridge/romstage/gpio_snr.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/fa21c1a5_14c26ac0?us… :
PS15, Line 160: */
> yes.
Done
File src/soc/intel/snowridge/systemagent.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/05eb0768_734c81b3?us… :
PS15, Line 33: {
> This pointer is passed from common system agent code, representing current assigned resources in sys […]
Done
File src/soc/intel/snowridge/systemagent.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/10ea0bc1_abbcf10d?us… :
PS21, Line 53: {
here we need to rename resource_cnt to resource_index as well.
https://review.coreboot.org/c/coreboot/+/83321/comment/63fd9a7c_0ef982ea?us… :
PS21, Line 77: &snr_configurable_resources[i].resources, 1);
here, can we omit the parameter '1'? a.k.a. for all cases, only one resource is added once.
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Change subject: mb/google/nissa/var/teliks: Update eMMC DLL tuning values
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: mb/google/brox/var/lotso: Configure cpu power limits by battery status
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Set Ready For Review
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