coreboot-gerrit September 2024

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PSYS setting
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: Add PSYS setting ...................................................................... mb/google/brask/var/bujia: Add PSYS setting According to the Intel OPS spec, the DC power from display is 12~19V@8A max. It can't set PsysPmax by unknown voltage, so get voltage by ec command "ectool adcread 4" then calculate PsysPmax value. The OPS display can supply 90W power, configure psys_pl2 to limit the system power to 90W. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W. Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/variants/bujia/Makefile.mk A src/mainboard/google/brya/variants/bujia/ramstage.c 2 files changed, 85 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/bujia/Makefile.mk b/src/mainboard/google/brya/variants/bujia/Makefile.mk index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/bujia/Makefile.mk +++ b/src/mainboard/google/brya/variants/bujia/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/bujia/ramstage.c b/src/mainboard/google/brya/variants/bujia/ramstage.c new file mode 100644 index 0000000..1aaa54b --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/ramstage.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 90 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 90 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 90 }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, 90 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 90 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 90 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in bujia, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 8A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 8A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.8 = 45.3K / (45.3K + 11.5K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 8A = 120W + * For Type-C 20V, the Psys_pmax should be 20v x 8A = 160W + * For a barrel jack, the Psys_pmax should be 20v x 8A = 160W + * + * Imagine that there is a Type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 160W. Then IMVP9.1 can calculate the current system + * power = 160W * 5A / 8A = 100W, which is the actual system power. + */ +struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 8000, + .bj_volts_mv = 12000 +}; + +static int32_t get_input_power_voltage(void) +{ + struct ec_params_adc_read req = { + .adc_channel = 4, + }; + struct ec_response_adc_read info; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_ADC_READ, + .cmd_size_in = sizeof(req), + .cmd_data_in = &req, + .cmd_size_out = sizeof(info), + .cmd_data_out = &info, + }; + if (!google_chromeec_command(&cmd)) + return psys_config.bj_volts_mv; + + return info.adc_value; +} + +void variant_devtree_update(void) +{ + psys_config.bj_volts_mv = get_input_power_voltage(); + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 16 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com>

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[XS] Change in coreboot[main]: vc/google/chromeos: Skip boot info logging if cse sync at payload
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84120?usp=email ) Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload ...................................................................... vc/google/chromeos: Skip boot info logging if cse sync at payload This patch skips event logging for current boot information at ramstage if CSE sync is scheduled at payload. Given that CSE sync could initiate a system reset, resulting in redundant boot information logs, the payload should handle the logging of boot information following CSE sync. BUG=b:360082747 TEST=Verified elog boot info is not logged at ramstage Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84120 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/google/chromeos/elog.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 4d3fc40..e60cec8 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -10,6 +10,13 @@ static void elog_add_vboot_info(void *unused) { + /* + * Skip logging boot info if CSE sync scheduled at payload. + * The payload should log boot info after CSE sync. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + /* Skip logging boot info in ACPI resume path */ if (acpi_is_wakeup_s3()) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/84120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50 Gerrit-Change-Number: 84120 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meminit: Check array size
by Arthur Heymans (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84205?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/meminit: Check array size ...................................................................... soc/intel/meminit: Check array size Work around a GCC LTO bug. Even if no buffer overflow is bound to happen as the soldered down path is taken GCC LTO complains about this. Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/memory/meminit.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84205/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Gerrit-Change-Number: 84205 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: include/assert.h: Deal with GCC LTO false positives
by Arthur Heymans (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84208?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: include/assert.h: Deal with GCC LTO false positives ...................................................................... include/assert.h: Deal with GCC LTO false positives With LTO GCC assert gets false positives, therefore disable the dead_code_t path in that case. Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/assert.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/84208/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... soc/mediatek/mt8196: Add EINT support Add support to configure GPIOs to pull for external interrupts (EINT). BUG=b:334723688 TEST=Talk with Ti50 TPM using IRQ flow. Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpio_eint.c M src/soc/mediatek/mt8196/include/soc/addressmap.h 3 files changed, 317 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index c8845ac..b11778f 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -3,7 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y) all-y += ../common/flash_controller.c -all-y += ../common/gpio.c ../common/gpio_op.c gpio.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += timer.c diff --git a/src/soc/mediatek/mt8196/gpio_eint.c b/src/soc/mediatek/mt8196/gpio_eint.c new file mode 100644 index 0000000..edbae73 --- /dev/null +++ b/src/soc/mediatek/mt8196/gpio_eint.c @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196_EINT_Datasheet + * Chapter number: 1 + */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> + +enum { + EINT_INVALID = 0, + EINT_E, + EINT_S, + EINT_W, + EINT_N, + EINT_C, +}; + +struct eint_info { + uint8_t instance; + uint8_t index; +}; + +static struct eint_info eint_data[] = { + /* instance, index */ + [0] = { EINT_W, 0 }, + [1] = { EINT_W, 1 }, + [2] = { EINT_W, 16 }, + [3] = { EINT_W, 17 }, + [4] = { EINT_W, 2 }, + [5] = { EINT_W, 3 }, + [6] = { EINT_W, 4 }, + [7] = { EINT_W, 5 }, + [8] = { EINT_W, 6 }, + [9] = { EINT_W, 18 }, + [10] = { EINT_W, 7 }, + [11] = { EINT_W, 8 }, + [12] = { EINT_W, 9 }, + [13] = { EINT_S, 4 }, + [14] = { EINT_E, 0 }, + [15] = { EINT_S, 5 }, + [16] = { EINT_S, 6 }, + [17] = { EINT_S, 7 }, + [18] = { EINT_S, 8 }, + [19] = { EINT_S, 9 }, + [20] = { EINT_E, 1 }, + [21] = { EINT_E, 10 }, + [22] = { EINT_E, 11 }, + [23] = { EINT_E, 12 }, + [24] = { EINT_E, 13 }, + [25] = { EINT_E, 14 }, + [26] = { EINT_E, 15 }, + [27] = { EINT_E, 2 }, + [28] = { EINT_E, 16 }, + [29] = { EINT_E, 17 }, + [30] = { EINT_E, 18 }, + [31] = { EINT_E, 3 }, + [32] = { EINT_E, 19 }, + [33] = { EINT_E, 20 }, + [34] = { EINT_E, 21 }, + [35] = { EINT_E, 22 }, + [36] = { EINT_E, 23 }, + [37] = { EINT_E, 24 }, + [38] = { EINT_E, 25 }, + [39] = { EINT_W, 10 }, + [40] = { EINT_W, 11 }, + [41] = { EINT_W, 12 }, + [42] = { EINT_W, 13 }, + [43] = { EINT_W, 14 }, + [44] = { EINT_W, 19 }, + [45] = { EINT_W, 20 }, + [46] = { EINT_W, 21 }, + [47] = { EINT_W, 22 }, + [48] = { EINT_W, 23 }, + [49] = { EINT_W, 24 }, + [50] = { EINT_W, 25 }, + [51] = { EINT_W, 26 }, + [60] = { EINT_W, 27 }, + [61] = { EINT_W, 28 }, + [62] = { EINT_W, 29 }, + [63] = { EINT_W, 30 }, + [64] = { EINT_W, 31 }, + [65] = { EINT_W, 32 }, + [70] = { EINT_W, 33 }, + [71] = { EINT_W, 34 }, + [72] = { EINT_W, 35 }, + [73] = { EINT_W, 36 }, + [74] = { EINT_W, 37 }, + [79] = { EINT_W, 38 }, + [80] = { EINT_W, 39 }, + [81] = { EINT_W, 40 }, + [82] = { EINT_W, 41 }, + [83] = { EINT_W, 42 }, + [84] = { EINT_W, 43 }, + [85] = { EINT_W, 44 }, + [86] = { EINT_W, 45 }, + [87] = { EINT_W, 46 }, + [88] = { EINT_W, 47 }, + [89] = { EINT_W, 48 }, + [90] = { EINT_W, 49 }, + [91] = { EINT_W, 50 }, + [92] = { EINT_W, 15 }, + [93] = { EINT_W, 51 }, + [94] = { EINT_W, 52 }, + [95] = { EINT_W, 53 }, + [96] = { EINT_W, 54 }, + [97] = { EINT_W, 55 }, + [98] = { EINT_W, 56 }, + [103] = { EINT_W, 57 }, + [106] = { EINT_S, 10 }, + [107] = { EINT_S, 11 }, + [108] = { EINT_S, 12 }, + [109] = { EINT_S, 13 }, + [110] = { EINT_S, 0 }, + [111] = { EINT_S, 1 }, + [112] = { EINT_S, 2 }, + [113] = { EINT_S, 3 }, + [114] = { EINT_S, 14 }, + [115] = { EINT_S, 15 }, + [116] = { EINT_S, 16 }, + [117] = { EINT_S, 17 }, + [118] = { EINT_S, 18 }, + [119] = { EINT_S, 19 }, + [120] = { EINT_S, 20 }, + [121] = { EINT_S, 21 }, + [122] = { EINT_S, 22 }, + [125] = { EINT_S, 23 }, + [126] = { EINT_S, 24 }, + [127] = { EINT_S, 25 }, + [128] = { EINT_S, 26 }, + [129] = { EINT_S, 27 }, + [130] = { EINT_S, 28 }, + [137] = { EINT_E, 26 }, + [138] = { EINT_E, 27 }, + [139] = { EINT_E, 28 }, + [140] = { EINT_E, 29 }, + [141] = { EINT_E, 30 }, + [142] = { EINT_E, 31 }, + [143] = { EINT_E, 32 }, + [144] = { EINT_E, 33 }, + [145] = { EINT_E, 34 }, + [146] = { EINT_E, 35 }, + [147] = { EINT_E, 36 }, + [148] = { EINT_E, 4 }, + [149] = { EINT_E, 37 }, + [150] = { EINT_E, 5 }, + [151] = { EINT_E, 38 }, + [152] = { EINT_E, 39 }, + [153] = { EINT_E, 40 }, + [154] = { EINT_E, 41 }, + [155] = { EINT_E, 42 }, + [156] = { EINT_E, 43 }, + [157] = { EINT_E, 44 }, + [158] = { EINT_E, 45 }, + [159] = { EINT_E, 46 }, + [160] = { EINT_E, 47 }, + [161] = { EINT_E, 48 }, + [162] = { EINT_E, 49 }, + [163] = { EINT_E, 50 }, + [164] = { EINT_E, 51 }, + [165] = { EINT_E, 52 }, + [166] = { EINT_E, 53 }, + [167] = { EINT_E, 54 }, + [168] = { EINT_E, 55 }, + [169] = { EINT_E, 56 }, + [170] = { EINT_E, 57 }, + [171] = { EINT_E, 58 }, + [172] = { EINT_E, 6 }, + [173] = { EINT_E, 7 }, + [174] = { EINT_E, 8 }, + [175] = { EINT_E, 9 }, + [178] = { EINT_E, 59 }, + [179] = { EINT_E, 60 }, + [180] = { EINT_E, 61 }, + [181] = { EINT_E, 62 }, + [182] = { EINT_E, 63 }, + [183] = { EINT_E, 64 }, + [184] = { EINT_E, 65 }, + [185] = { EINT_E, 66 }, + [186] = { EINT_N, 6 }, + [187] = { EINT_N, 7 }, + [192] = { EINT_N, 8 }, + [193] = { EINT_N, 9 }, + [196] = { EINT_N, 10 }, + [197] = { EINT_N, 11 }, + [204] = { EINT_N, 12 }, + [205] = { EINT_N, 13 }, + [206] = { EINT_N, 14 }, + [207] = { EINT_N, 0 }, + [208] = { EINT_N, 1 }, + [209] = { EINT_N, 2 }, + [210] = { EINT_N, 15 }, + [211] = { EINT_N, 3 }, + [212] = { EINT_N, 4 }, + [213] = { EINT_N, 5 }, + [216] = { EINT_N, 16 }, + [217] = { EINT_N, 17 }, + [218] = { EINT_N, 18 }, + [219] = { EINT_N, 19 }, + [220] = { EINT_N, 20 }, + [221] = { EINT_N, 21 }, + [222] = { EINT_N, 22 }, + [223] = { EINT_N, 23 }, + [224] = { EINT_N, 24 }, + [225] = { EINT_N, 25 }, + [226] = { EINT_N, 26 }, + [227] = { EINT_N, 27 }, + [228] = { EINT_N, 28 }, + [229] = { EINT_N, 29 }, + [241] = { EINT_N, 30 }, + [242] = { EINT_N, 31 }, + [243] = { EINT_N, 32 }, + [245] = { EINT_N, 45 }, + [251] = { EINT_E, 67 }, + [252] = { EINT_E, 68 }, + [253] = { EINT_E, 69 }, + [254] = { EINT_E, 70 }, + [255] = { EINT_E, 71 }, + [256] = { EINT_E, 72 }, + [257] = { EINT_E, 73 }, + [258] = { EINT_E, 74 }, + [259] = { EINT_N, 33 }, + [260] = { EINT_N, 34 }, + [261] = { EINT_N, 35 }, + [262] = { EINT_N, 36 }, + [263] = { EINT_N, 37 }, + [264] = { EINT_N, 38 }, + [265] = { EINT_N, 39 }, + [266] = { EINT_N, 40 }, + [267] = { EINT_N, 41 }, + [268] = { EINT_N, 42 }, + [269] = { EINT_N, 43 }, + [270] = { EINT_N, 44 }, + [271] = { EINT_C, 0 }, + [272] = { EINT_C, 1 }, + [273] = { EINT_C, 2 }, + [274] = { EINT_C, 3 }, + [275] = { EINT_C, 4 }, + [276] = { EINT_C, 5 }, + [277] = { EINT_C, 6 }, + [278] = { EINT_C, 7 }, + [279] = { EINT_C, 8 }, + [280] = { EINT_C, 9 }, + [281] = { EINT_C, 10 }, + [282] = { EINT_C, 11 }, + [283] = { EINT_C, 12 }, + [284] = { EINT_C, 13 }, + [285] = { EINT_C, 14 }, + [286] = { EINT_C, 15 }, + [287] = { EINT_C, 16 }, + [288] = { EINT_C, 17 }, + [289] = { EINT_C, 18 }, + [290] = { EINT_C, 19 }, + [291] = { EINT_C, 20 }, + [292] = { EINT_C, 21 }, +}; +_Static_assert(ARRAY_SIZE(eint_data) == 293); + +void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit) +{ + uint32_t idx = gpio.id; + + *pos = 0; + *bit = 0; + + if (idx >= ARRAY_SIZE(eint_data)) + return; + + uint8_t index = eint_data[idx].index; + + *pos = index / MAX_EINT_REG_BITS; + *bit = index % MAX_EINT_REG_BITS; +} + +struct eint_regs *gpio_get_eint_reg(gpio_t gpio) +{ + uint32_t idx = gpio.id; + uintptr_t addr; + + if (idx >= ARRAY_SIZE(eint_data)) + return NULL; + + switch (eint_data[idx].instance) { + case EINT_E: + addr = EINT_E_BASE; + break; + case EINT_S: + addr = EINT_S_BASE; + break; + case EINT_W: + addr = EINT_W_BASE; + break; + case EINT_N: + addr = EINT_N_BASE; + break; + case EINT_C: + addr = EINT_C_BASE; + break; + default: + printk(BIOS_ERR, "%s: Failed to look up a valid EINT base for %d\n", + __func__, idx); + return NULL; + } + + return (void *)addr; +} diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 67faa0e..c50ab6e 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -14,6 +14,14 @@ }; enum { + EINT_E_BASE = IO_PHYS + 0x02080000, + EINT_S_BASE = IO_PHYS + 0x02880000, + EINT_W_BASE = IO_PHYS + 0x03080000, + EINT_N_BASE = IO_PHYS + 0x03880000, + EINT_C_BASE = IO_PHYS + 0x0C54A000, +}; + +enum { CKSYS_BASE = IO_PHYS + 0x00000000, APMIXED_BASE = IO_PHYS + 0x00000800, INFRACFG_AO_BASE = IO_PHYS + 0x00001000, @@ -103,7 +111,6 @@ SPMI_MST_BASE = IO_PHYS + 0x0C01C000, SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, SYSTIMER_BASE = IO_PHYS + 0x0C400000, - EINT_BASE = IO_PHYS + 0x0C54A000, DSI0_BASE = IO_PHYS + 0x22490000, DISP_DVO0 = IO_PHYS + 0x224C0000, EDP_BASE = IO_PHYS + 0x2EC40000, -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 22 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84211?usp=email ) Change subject: mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM ...................................................................... mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM Add control for the 1.2V enable pin in VCM to comply the mipi camera power sequence. 2.8V enable --> 1.2V enable --> reset BUG=b:362386165 TEST=Run ITS test Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/yavilla/overridetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index ee5a3b6..973a16b 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -404,17 +404,20 @@ #Controls register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D3" # WCAM_RST_L + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "2" + register "on_seq.ops_cnt" = "3" register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF - register "off_seq.ops_cnt" = "2" + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 0C on probe WFC WFC_MIPI_OVTI8856 -- To view, visit https://review.coreboot.org/c/coreboot/+/84211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Gerrit-Change-Number: 84211 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: Makefile.mk: compile ECC tools and inject ECC to final image
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67064?usp=email ) ( 40 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Makefile.mk: compile ECC tools and inject ECC to final image ...................................................................... Makefile.mk: compile ECC tools and inject ECC to final image $ build/cbfstool build/coreboot.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed) fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed) config 0xa880 raw 1324 LZMA (3308 decompressed) revision 0xae00 raw 726 none build_info 0xb100 raw 122 none (empty) 0xb1c0 null 347108 none header_pointer 0x5fdc0 cbfs header 4 none Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67064 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M src/soc/ibm/power9/Makefile.mk 2 files changed, 14 insertions(+), 2 deletions(-) Approvals: Paul Menzel: Looks good to me, approved build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve diff --git a/Makefile.mk b/Makefile.mk index e7a9ab1..2b67947 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -636,7 +636,7 @@ additional-dirs += $(objutil)/cbfstool $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ - $(objutil)/cbootimage + $(objutil)/cbootimage $(objutil)/ffs export $(COREBOOT_EXPORTS) @@ -678,6 +678,7 @@ AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress CSE_FPT:=$(objutil)/cbfstool/cse_fpt CSE_SERGER:=$(objutil)/cbfstool/cse_serger +ECCTOOL:=$(objutil)/ffs/ecc/ecc $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -719,6 +720,12 @@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool AMDFWREAD:=$(objutil)/amdfwtool/amdfwread +$(ECCTOOL): + @printf " Compile ECCTOOL\n" + cp -r $(top)/3rdparty/ffs $(objutil) + cd $(objutil)/ffs && autoreconf -i && ./configure + $(MAKE) -C $(objutil)/ffs + APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py @@ -829,7 +836,7 @@ include util/crossgcc/Makefile.mk .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) ########################################################################### # Common recipes for all stages diff --git a/src/soc/ibm/power9/Makefile.mk b/src/soc/ibm/power9/Makefile.mk index 84a40f9..f0ce2ea 100644 --- a/src/soc/ibm/power9/Makefile.mk +++ b/src/soc/ibm/power9/Makefile.mk @@ -14,4 +14,9 @@ ramstage-y += rom_media.c ramstage-y += timer.c +files_added:: $(obj)/coreboot.rom.ecc + +$(obj)/coreboot.rom.ecc: $(obj)/coreboot.rom | $(ECCTOOL) + $(ECCTOOL) --inject $< --output $@ --p8 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/67064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d Gerrit-Change-Number: 67064 Gerrit-PatchSet: 42 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao. Felix Held has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 13:22:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: amdfwtool: Set L2 table size as 0x400
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Marshall Dawson, Zheng Bao, ritul guru. Felix Held has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84194?usp=email ) Change subject: amdfwtool: Set L2 table size as 0x400 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Gerrit-Change-Number: 84194 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Sep 2024 13:21:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: remove unused cam enable_gpio
by Felix Held (Code Review) 06 Sep '24

06 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84198?usp=email ) Change subject: mb/google/brox/var/lotso: remove unused cam enable_gpio ...................................................................... mb/google/brox/var/lotso: remove unused cam enable_gpio Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/lotso/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 09e8815..85a3506 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -281,8 +281,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" device ref usb2_port6 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/84198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8 Gerrit-Change-Number: 84198 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com>

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coreboot-gerrit September 2024