Hello Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: amdfwtool: Add combo new layout for new family
......................................................................
amdfwtool: Add combo new layout for new family
The new layout definition has a new way to support combo.
It packs multiple ISH entries into PSP L1 directory.
TEST=Identical test on all AMD platform
Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 22 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84233/3
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Gerrit-Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757
Gerrit-Change-Number: 84233
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Bao Zheng has restored this change. ( https://review.coreboot.org/c/coreboot/+/84233?usp=email )
Change subject: amdfwtool: Add combo new layout for new family
......................................................................
Restored
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Matt DeVillier has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84195/comment/5b7e316f_94271e39?us… :
PS3, Line 22: /disable
nit: based on the code change, it appears that 'no recovery' is the default, and the flag is passed to enable (but not disable) the A/B recovery scheme.
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Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )
Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
......................................................................
Patch Set 4: Code-Review+1
(10 comments)
Patchset:
PS2:
> i think we also support odroid-h4 plus too, should you add this as another variant?
What are the differences? If possible I'd try to avoid creating variants (different firmware builds) and instead have the same coreboot target for H4, H4 plus and whatever
File src/mainboard/hardkernel/odroid-h4/Kconfig:
https://review.coreboot.org/c/coreboot/+/83979/comment/5d0806d3_081cff3b?us… :
PS4, Line 37: config NO_POST
: default y
:
There's a FFC (Flat Flexible Cable) connector on the bottom of the board named "ESPI_DEBUG1", so I would keep POST codes enabled in case someone needs them to debug.
File src/mainboard/hardkernel/odroid-h4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/ecab88b1_2f372e70?us… :
PS4, Line 13: ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10
What is GP10 used for? Seems unused on both schematics and in vendor firmware default settings (0x00, same as chip default). Please remove
https://review.coreboot.org/c/coreboot/+/83979/comment/9c91ab83_738f1d21?us… :
PS4, Line 14: ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31
GP31 is used as CTS# so this should be removed too
https://review.coreboot.org/c/coreboot/+/83979/comment/84009726_e4393a4a?us… :
PS4, Line 15: ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40
This seems to be used as PWRGD3, going to SYS_PWROK. I think this should be removed.
https://review.coreboot.org/c/coreboot/+/83979/comment/360e260e_38a15045?us… :
PS4, Line 16: Enable Pin GP50
This is not GP50 (doesn't appear in the schematics), but the value matches vendor firmware.
File src/mainboard/hardkernel/odroid-h4/gpio.h:
https://review.coreboot.org/c/coreboot/+/83979/comment/96b25019_e42b3db7?us… :
PS4, Line 96: PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */
This is not used
File src/mainboard/hardkernel/odroid-h4/ramstage_fsp_params.c:
PS4:
No license header
https://review.coreboot.org/c/coreboot/+/83979/comment/22b87964_407e1fa0?us… :
PS4, Line 4:
: fsp_s_config->PchLegacyIoLowLatency = 1;
: fsp_s_config->PchDmiAspmCtrl = 0;
Why?
File src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/8463c89f_78647279?us… :
PS4, Line 29: TODO: Implement __weak variant_is_half_populated(void) function.
Copy-pasta? This board has no variants, so this doesn't make much sense
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Attention is currently required from: Arthur Heymans.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84033?usp=email
to look at the new patch set (#35).
Change subject: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO
......................................................................
[NOT_FOR_MERGE]Kconfig: Build all targets with LTO
ARM, RISCV and PPC64 with GCC LTO fails hard.
Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84033/35
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83997?usp=email )
Change subject: soc/intel/common/gpio: vm index changes as PTL vm entries are not continuous
......................................................................
soc/intel/common/gpio: vm index changes as PTL vm entries are not continuous
Add specific virtual wire mapping structure for:
- First pad group does not starts with bit position 0.
- vw_index and position are not continuous in between groups within a
community.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
2 files changed, 17 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index d49742d..625c3f4 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -1068,8 +1068,16 @@
if (i == comm->num_vw_entries)
return false;
- offset += pad - comm->vw_entries[i].first_pad;
- *vw_index = comm->vw_base + offset / 8;
+ /* Adjust offset and calculate vw_index based on the mapping type */
+ if (comm->vw_map) {
+ offset = pad - comm->vw_entries[i].first_pad;
+ offset += comm->vw_map[i].start_pos;
+ *vw_index = comm->vw_map[i].base + offset / 8;
+ } else {
+ offset += pad - comm->vw_entries[i].first_pad;
+ offset += comm->vw_base;
+ *vw_index = offset / 8;
+ }
*vw_bit = offset % 8;
return true;
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 39d17a1..a501f7f 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -110,6 +110,12 @@
gpio_t last_pad;
};
+/* virtual-wire mapping base and the starting bit position for a group */
+struct vw_map {
+ uint8_t base;
+ uint8_t start_pos;
+};
+
/* This structure will be used to describe a community or each group within a
* community when multiple groups exist inside a community
*/
@@ -152,6 +158,7 @@
* which they map to VW indexes (beginning with VW base)
*/
const struct vw_entries *vw_entries;
+ const struct vw_map *vw_map;
size_t num_vw_entries;
};
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