coreboot-gerrit September 2024

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[S] Change in coreboot[main]: util/cbfstool: Add Intel platform boot policy support
by Shuo Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Chen, Gang C, Jincheng Li. Hello Chen, Gang C, Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84305?usp=email to review the following change. Change subject: util/cbfstool: Add Intel platform boot policy support ...................................................................... util/cbfstool: Add Intel platform boot policy support Intel platform boot policy setting blob is linked into FIT table as an FIT4 entry. Please refer to chapter 4.6 of the document in below link: https://www.intel.com/content/dam/www/public/us/en/documents/ guides/fit-bios-specification.pdf Tool usage: ./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \ -r COREBOOT -s <max table size> Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/cpu/intel/fit/Makefile.mk M src/southbridge/intel/common/firmware/Kconfig M util/cbfstool/fit.c M util/cbfstool/fit.h 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84305/1 diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk index a86a22e..f405c57 100644 --- a/src/cpu/intel/fit/Makefile.mk +++ b/src/cpu/intel/fit/Makefile.mk @@ -50,4 +50,17 @@ endif # CONFIG_CPU_MICROCODE_CBFS_NONE +# Platform Boot Policy +ifeq ($(CONFIG_HAVE_PBP_BIN),y) + +cbfs-files-y += pbp.bin +pbp.bin-file := $(call strip_quotes,$(CONFIG_PBP_BIN_PATH)) +pbp.bin-type := raw + +$(call add_intermediate, add_pbp_fit, set_fit_ptr $(IFITTOOL)) + @printf " UPDATE-FIT Platform Boot Policy binary\n" + $(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT + +endif # CONFIG_HAVE_PBP_BIN + endif # CONFIG_UPDATE_IMAGE diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 95eda31..a91d550 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -24,6 +24,17 @@ default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN +config HAVE_PBP_BIN + bool "Add Intel platform boot policy file" + default n + help + The platform boot policy file + +config PBP_BIN_PATH + string "Path and filename of the platform boot policy file" + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/pbp.bin" + depends on HAVE_PBP_BIN + config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 8ed2494..888fd30 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -17,6 +17,7 @@ #define FIT_HEADER_VERSION 0x0100 #define FIT_HEADER_ADDRESS "_FIT_ " #define FIT_MICROCODE_VERSION 0x0100 +#define FIT_PLATFORM_BOOT_POLICY_VERSION 0x0100 #define FIT_TXT_VERSION 0x0100 #define FIT_SIZE_ALIGNMENT 16 @@ -367,6 +368,18 @@ fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); } +static void update_fit_pbp_entry(struct fit_table *fit, + struct fit_entry *entry, + const uint64_t pbp_addr) +{ + entry->address = pbp_addr; + entry->size_reserved = 0; + entry->type_checksum_valid = FIT_TYPE_PLATFORM_BOOT_POLICY; + entry->version = FIT_PLATFORM_BOOT_POLICY_VERSION; + entry->checksum = 0; + fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); +} + /* * In case there's a FIT_TYPE_BIOS_ACM entry, at least one * FIT_TYPE_BIOS_STARTUP entry must exist. @@ -607,6 +620,9 @@ case FIT_TYPE_BIOS_ACM: name = "BIOS ACM"; break; + case FIT_TYPE_PLATFORM_BOOT_POLICY: + name = "Platform Boot Policy"; + break; case FIT_TYPE_BIOS_STARTUP: name = "BIOS Startup Module"; break; @@ -676,6 +692,7 @@ switch (type) { case FIT_TYPE_MICROCODE: case FIT_TYPE_BIOS_ACM: + case FIT_TYPE_PLATFORM_BOOT_POLICY: case FIT_TYPE_BIOS_STARTUP: case FIT_TYPE_BIOS_POLICY: case FIT_TYPE_TXT_POLICY: @@ -728,6 +745,9 @@ case FIT_TYPE_BIOS_ACM: update_fit_bios_acm_entry(fit, entry, offset); break; + case FIT_TYPE_PLATFORM_BOOT_POLICY: + update_fit_pbp_entry(fit, entry, offset); + break; case FIT_TYPE_BIOS_STARTUP: update_fit_bios_startup_entry(fit, entry, offset, len); break; diff --git a/util/cbfstool/fit.h b/util/cbfstool/fit.h index a0c956c..6d7681f 100644 --- a/util/cbfstool/fit.h +++ b/util/cbfstool/fit.h @@ -15,6 +15,7 @@ FIT_TYPE_HEADER = 0, FIT_TYPE_MICROCODE = 1, FIT_TYPE_BIOS_ACM = 2, + FIT_TYPE_PLATFORM_BOOT_POLICY = 4, FIT_TYPE_BIOS_STARTUP = 7, FIT_TYPE_TPM_POLICY = 8, FIT_TYPE_BIOS_POLICY = 9, -- To view, visit https://review.coreboot.org/c/coreboot/+/84305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Gerrit-Change-Number: 84305 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources
by Shuo Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84304?usp=email ) Change subject: soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources ...................................................................... soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources On GNR, there are CXL Type-3 memory window covered under TOHM. The current 4GB to TOHM DRAM reporting doesn't work no GNR. Use MemoryMapDataHob to add high RAM resources as a generic mechanism for GNR and previous generation SoCs. Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84304/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index be5b38f..22f7e8e 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,21 +284,25 @@ mc_values[TOLM_REG]); LOG_RESOURCE("mmio_tolm", dev, res); - if (CONFIG(SOC_INTEL_HAS_CXL)) { - /* 4GiB -> CXL Memory */ - uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ - /* - * Memory layout when there is CXL HDM (Host-managed Device Memory): - * -------------- <- TOHM - * CXL memory regions (pds global variable records the base/size of them) - * Processor attached high memory - * -------------- <- 0x100000000 (4GB) - */ - res = upper_ram_end(dev, index++, - mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); - LOG_RESOURCE("high_ram", dev, res); + /* Add high RAM */ + const struct SystemMemoryMapHob *mm = get_system_memory_map(); + for (int i = 0; i < mm->numberEntries; i++) { + const struct SystemMemoryMapElement *e = &mm->Element[i]; + uint64_t addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); + if (addr < 4ULL * GiB) + continue; + if (!is_memtype_processor_attached(e->Type)) + continue; + if (is_memtype_reserved(e->Type)) + continue; + + res = ram_range(dev, index++, addr, size); + LOG_RESOURCE("high_ram", dev, res); + } + + if (CONFIG(SOC_INTEL_HAS_CXL)) { /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { @@ -320,10 +324,6 @@ else LOG_RESOURCE("CXL_memory", dev, res); } - } else { - /* 4GiB -> TOHM */ - res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1); - LOG_RESOURCE("high_ram", dev, res); } /* add MMIO CFG resource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Gerrit-Change-Number: 84304 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[L] Change in coreboot[main]: vc/intel/fsp/fsp2_0/graniterapids: Update FSP headers
by Shuo Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84303?usp=email to review the following change. Change subject: vc/intel/fsp/fsp2_0/graniterapids: Update FSP headers ...................................................................... vc/intel/fsp/fsp2_0/graniterapids: Update FSP headers FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to pass compilation with full platform codes. Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h M src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h 12 files changed, 304 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84303/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h index 7338538..6d5ba0a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h @@ -31,4 +31,10 @@ #ifndef _FSP_ACPI_HOBS_H_ #define _FSP_ACPI_HOBS_H_ +//Typecast HOB pointer to ACPI CXL CEDT table structure +#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } } + +//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA; +#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } } + #endif //#ifndef _FSP_ACPI_HOBS_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h new file mode 100644 index 0000000..af0dc50 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_EDPC_PARAM__ +#define __FSP_EDPC_PARAM__ + +#pragma pack(1) +typedef struct { + UINT8 Segment; + UINT8 Bus; + UINT8 Device; + UINT8 Function; +} EDPC_DEV_INFO; + +typedef struct { + // + // There are three possible statuses of Valid infomation + // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED + // + UINT8 Valid; + EDPC_DEV_INFO EdpcTrigger; + EDPC_DEV_INFO EdpcRootPort; + UINT8 NotifyType; +} EDPC_INFO; + +typedef struct { + UINT16 OsNativeAerSupport; + UINT16 Reserved; + UINT64 Reserved1[400]; + EDPC_INFO EdpcInfo; + UINT64 EmcaL1DirAddr; + UINT8 EmcaEn; + UINT8 ElogEn; + UINT8 WheaEnabled; + UINT8 WheaSupportEn; + UINT64 ReadAckAddress; + UINT64 OobReadAckAddress; + UINT32 SoftwareSmi; +} RAS_ACPI_PARAM; + +#pragma pack() +#endif // __FSP_EDPC_PARAM__ diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h index 93ca558..77133a7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h @@ -41,6 +41,40 @@ typedef struct { + /** WHEA Support + Enable/Disable WHEA support. + 0:Disable, 1:Enable +**/ + UINT8 WheaSupportEn; + +/** Enable/Disable WHEA Error Injection Support. + 0:Disabled, 1:Enabled +**/ + UINT8 WheaErrorInjSupportEn; + +/** Whea EINJ ACPI 5.0 support for set error type with address and vendor extensions. + 0:Disabled, 1:Enabled +**/ + UINT8 WheaACPI50ErrInjEn; + +/** Whea PCIE Error Injection Support + Enable/Disable Whea PCIE Error Injection Support in FSP. + 0:Disable, 1:Enable +**/ + UINT8 WheaPcieErrInjEn; + +/** Whea PCIe Error Injection Action Table + Use Action Table for Whea PCIe Error Injection in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcieErrInjActionTable; + +/** IIO eDPC Support + Enable/Disable IIO eDPC Support. + 0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors +**/ + UINT8 EdpcEn; + /** N/A **/ UINT8 ReservedSiliconInitUpd[16]; diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h index 65c2a42..f71bc04 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h @@ -47,12 +47,28 @@ #define MAX_IOU_PER_SOCKET 7 #endif +#ifndef MAX_IIO_PORTS_PER_STACK +#define MAX_IIO_PORTS_PER_STACK 1 +#endif + + +#define MAX_IIO_PCIE_PER_SOCKET 1 + #define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD #pragma pack(1) typedef enum { PE0 = 0, + PE1, + PE2, + PE3, + PE4, + PE5, + PEa, + PEb, + PEc, + PEd, PE_MAX, PE_ = 0xFF // temporary unknown value } IIO_PACKAGE_PE; @@ -112,15 +128,27 @@ } IIO_SLOT_CFG; typedef struct { + UINT8 Address; // SMBUS address of IO expander which provides NPEM + UINT8 Bank; // Port or bank on IoExpander which provides NPEM + UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM + UINT8 MuxChannel; // Channel of the MUX used to access NPEM +} IIO_NPEM_CFG; + +typedef struct { IIO_VPP_CFG Vpp; + IIO_NPEM_CFG Npem; IIO_SLOT_CFG Slot; UINT8 VppEnabled :1; UINT8 VppExpType :1; + UINT8 NpemSupported :1; UINT8 SlotImplemented :1; - UINT8 Reserved :4; + UINT8 Retimer1Present :1; + UINT8 Retimer2Present :1; + UINT8 CommonClock :1; + UINT8 SRIS :1; UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port @@ -212,6 +240,9 @@ #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 #define IIO_BIFURCATE_AUTO 0xFF +#define C1_UID 2 +#define C2_UID 3 + typedef enum { IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx, IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4, diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h index 1689a42..6b4fa35 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h @@ -74,9 +74,6 @@ #define MAX_IIO_PORTS_PER_STACK 8 #endif -#ifndef MAX_IIO_PCIE_PER_SOCKET -#define MAX_IIO_PCIE_PER_SOCKET 1 -#endif #ifndef MAX_IIO_PCIROOTS_PER_STACK #define MAX_IIO_PCIROOTS_PER_STACK 1 @@ -217,6 +214,7 @@ UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK]; UINT64 VtbarAddress; // VT-d Base Address + UINT64 ChbcrBarAddress; } UDS_STACK_RES; typedef struct { @@ -261,6 +259,14 @@ UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0] QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + UINT16 SystemIoBase; // System IO Base + UINT16 SystemIoLimit; // System IO Limit + UINT32 SystemMmio32Base; // System low MMIO base + UINT32 SystemMmio32Limit; + UINT32 Mmio32Granularity; + UINT64 SystemMmio64Base; // System high MMIO Base + UINT64 SystemMmio64Limit; // System high MMIO Limit + UINT64 Mmio64Granularity; UINT32 MemTsegSize; UINT64 PciExpressBase; UINT32 PciExpressSize; diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h index ce47106..ad3eec3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h @@ -235,6 +235,8 @@ MemTypeCxlExpPersistentMem, MemTypeCxl2lmDdrCacheMem, MemTypeCxlHetero, + MemTypeCxlAccVolatileMemHdmDb, + MemTypeCxlExpVolatileMemDcd, MemTypeMax } MEM_TYPE; diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h index 7338538..6d5ba0a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h @@ -31,4 +31,10 @@ #ifndef _FSP_ACPI_HOBS_H_ #define _FSP_ACPI_HOBS_H_ +//Typecast HOB pointer to ACPI CXL CEDT table structure +#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } } + +//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA; +#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } } + #endif //#ifndef _FSP_ACPI_HOBS_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h new file mode 100644 index 0000000..af0dc50 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_EDPC_PARAM__ +#define __FSP_EDPC_PARAM__ + +#pragma pack(1) +typedef struct { + UINT8 Segment; + UINT8 Bus; + UINT8 Device; + UINT8 Function; +} EDPC_DEV_INFO; + +typedef struct { + // + // There are three possible statuses of Valid infomation + // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED + // + UINT8 Valid; + EDPC_DEV_INFO EdpcTrigger; + EDPC_DEV_INFO EdpcRootPort; + UINT8 NotifyType; +} EDPC_INFO; + +typedef struct { + UINT16 OsNativeAerSupport; + UINT16 Reserved; + UINT64 Reserved1[400]; + EDPC_INFO EdpcInfo; + UINT64 EmcaL1DirAddr; + UINT8 EmcaEn; + UINT8 ElogEn; + UINT8 WheaEnabled; + UINT8 WheaSupportEn; + UINT64 ReadAckAddress; + UINT64 OobReadAckAddress; + UINT32 SoftwareSmi; +} RAS_ACPI_PARAM; + +#pragma pack() +#endif // __FSP_EDPC_PARAM__ diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h index 93ca558..5aa10ee 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h @@ -41,6 +41,40 @@ typedef struct { +/** WHEA Support + Enable/Disable WHEA support. + 0:Disable, 1:Enable +**/ + UINT8 WheaSupportEn; + +/** Enable/Disable WHEA Error Injection Support. + 0:Disabled, 1:Enabled +**/ + UINT8 WheaErrorInjSupportEn; + +/** Whea EINJ ACPI 5.0 support for set error type with address and vendor extensions. + 0:Disabled, 1:Enabled +**/ + UINT8 WheaACPI50ErrInjEn; + +/** Whea PCIE Error Injection Support + Enable/Disable Whea PCIE Error Injection Support in FSP. + 0:Disable, 1:Enable +**/ + UINT8 WheaPcieErrInjEn; + +/** Whea PCIe Error Injection Action Table + Use Action Table for Whea PCIe Error Injection in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcieErrInjActionTable; + +/** IIO eDPC Support + Enable/Disable IIO eDPC Support. + 0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors +**/ + UINT8 EdpcEn; + /** N/A **/ UINT8 ReservedSiliconInitUpd[16]; diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h index 65c2a42..53dd0ea 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h @@ -47,17 +47,40 @@ #define MAX_IOU_PER_SOCKET 7 #endif +#ifndef MAX_IIO_PORTS_PER_STACK +#define MAX_IIO_PORTS_PER_STACK 1 +#endif + + +#define MAX_IIO_PCIE_PER_SOCKET 1 + #define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD #pragma pack(1) typedef enum { PE0 = 0, + PE1, + PE2, + PE3, + PE4, + PE5, + PEa, + PEb, + PEc, + PEd, PE_MAX, PE_ = 0xFF // temporary unknown value } IIO_PACKAGE_PE; typedef struct { + UINT8 Address; // SMBUS address of IO expander which provides NPEM + UINT8 Bank; // Port or bank on IoExpander which provides NPEM + UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM + UINT8 MuxChannel; // Channel of the MUX used to access NPEM +} IIO_NPEM_CFG; + +typedef struct { UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) @@ -114,13 +137,18 @@ typedef struct { IIO_VPP_CFG Vpp; + IIO_NPEM_CFG Npem; IIO_SLOT_CFG Slot; UINT8 VppEnabled :1; UINT8 VppExpType :1; + UINT8 NpemSupported :1; UINT8 SlotImplemented :1; - UINT8 Reserved :4; + UINT8 Retimer1Present :1; + UINT8 Retimer2Present :1; + UINT8 CommonClock :1; + UINT8 SRIS :1; UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port @@ -212,6 +240,9 @@ #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 #define IIO_BIFURCATE_AUTO 0xFF +#define C1_UID 2 +#define C2_UID 3 + typedef enum { IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx, IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4, diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h index 1689a42..6631a39 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h @@ -74,10 +74,6 @@ #define MAX_IIO_PORTS_PER_STACK 8 #endif -#ifndef MAX_IIO_PCIE_PER_SOCKET -#define MAX_IIO_PCIE_PER_SOCKET 1 -#endif - #ifndef MAX_IIO_PCIROOTS_PER_STACK #define MAX_IIO_PCIROOTS_PER_STACK 1 #endif @@ -217,6 +213,7 @@ UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK]; UINT64 VtbarAddress; // VT-d Base Address + UINT64 ChbcrBarAddress; } UDS_STACK_RES; typedef struct { @@ -261,6 +258,14 @@ UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0] QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + UINT16 SystemIoBase; // System IO Base + UINT16 SystemIoLimit; // System IO Limit + UINT32 SystemMmio32Base; // System low MMIO base + UINT32 SystemMmio32Limit; + UINT32 Mmio32Granularity; + UINT64 SystemMmio64Base; // System high MMIO Base + UINT64 SystemMmio64Limit; // System high MMIO Limit + UINT64 Mmio64Granularity; UINT32 MemTsegSize; UINT64 PciExpressBase; UINT32 PciExpressSize; diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h index ce47106..ad3eec3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h @@ -235,6 +235,8 @@ MemTypeCxlExpPersistentMem, MemTypeCxl2lmDdrCacheMem, MemTypeCxlHetero, + MemTypeCxlAccVolatileMemHdmDb, + MemTypeCxlExpVolatileMemDcd, MemTypeMax } MEM_TYPE; -- To view, visit https://review.coreboot.org/c/coreboot/+/84303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48 Gerrit-Change-Number: 84303 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE
by Shuo Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Chen, Gang C. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84302?usp=email to review the following change. Change subject: soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE ...................................................................... soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR, this default size is enough. Use the default size so that more CAR spaces could be saved for other purpose. Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Kconfig 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/84302/1 diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig index 790f20e..fae9d8d 100644 --- a/src/soc/intel/xeon_sp/gnr/Kconfig +++ b/src/soc/intel/xeon_sp/gnr/Kconfig @@ -56,15 +56,6 @@ and/or romstage. FSP-T reserves the upper 0x100 for FspReservedBuffer. -config DCACHE_BSP_STACK_SIZE - hex - default 0x60000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. It needs to include FSP-M stack requirement and - CB romstage stack requirement. The integration documentation - says this needs to be 256KiB. - config FSP_M_RC_HEAP_SIZE hex default 0x142000 -- To view, visit https://review.coreboot.org/c/coreboot/+/84302?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Gerrit-Change-Number: 84302 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com>

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[S] Change in coreboot[main]: make same cpu pyhsical address
by Wonkyu Kim (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Lance Zhao, Subrata Banik, Tim Wawrzynczak. Wonkyu Kim has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84230?usp=email ) Change subject: make same cpu pyhsical address ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > If I remember well, CPU Physical Address size and SoC physic Address size can be different. […] Yes. This is same case. The concern is that FSP uses 42 and coreboot reports 42 to OS in DMAR table while coreboot still use 46 in some of module. So, the concern is coreboot is using both 46 and 42 as physical address width if CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH is defined as 42 while cpu register reports 46. -- To view, visit https://review.coreboot.org/c/coreboot/+/84230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 Gerrit-Change-Number: 84230 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 01:15:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: src/device: Add more condition to check valid PCI device id
by Wonkyu Kim (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jeremy Compostella, Pratikkumar V Prajapati, Subrata Banik. Wonkyu Kim has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84228?usp=email ) Change subject: src/device: Add more condition to check valid PCI device id ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84228/comment/a63aa8a3_afdf3b20?us… : PS2, Line 12: Below are invalid PCI device id cases : VID: 0x0 or 0xffff : DID: 0x0 or 0xffff > > I think it does not harm to add more condition and DID 0x0 and 0xffff are not valid . […] The change is not just WA but also avoiding coreboot's weird behavior. The issue should be fixed by HW but I think coreboot should not stuck middle of execution without reporting error at least. -- To view, visit https://review.coreboot.org/c/coreboot/+/84228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffabc9037a8af1b2a4ffebdf30199c4f6eae9540 Gerrit-Change-Number: 84228 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 01:10:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[XS] Change in coreboot[main]: intel/cmm/block: use CONFIG_SMM_TSEG_SIZE in sa_get_tseg_size function
by Wonkyu Kim (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jeremy Compostella, Jérémy Compostella, Paul Menzel, Subrata Banik. Wonkyu Kim has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84210?usp=email ) Change subject: intel/cmm/block: use CONFIG_SMM_TSEG_SIZE in sa_get_tseg_size function ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/84210/comment/51620cdb_b27f0321?us… : PS2, Line 155: return sa_get_gsm_base() - sa_get_tseg_base(); > > We checked internally and got recommendation not to calculate it as CONFIG_SMM_TSEG_SIZE is passed […] FSP team mentioned that Tseg size is passed by UPD and memory map(relationship for Tesg base and gsm base) can also be changed in future silicon. So, FSP team recommend use Tseg size which is passed to UPD which is CONFIG_SMM_TSEG_SIZE. File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/84210/comment/7256a005_c963df5b?us… : PS3, Line 151: if (CONFIG_SMM_TSEG_SIZE) { : return CONFIG_SMM_TSEG_SIZE; : } : > what is this for ? If CONFIG_SMM_TSEG_SIZE is defined use CONFIG_SMM_TSEG_SIZE rather than calculation. -- To view, visit https://review.coreboot.org/c/coreboot/+/84210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3d5175add1f7dc6e2c9f1c38133b36ffc59e789 Gerrit-Change-Number: 84210 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Sep 2024 01:03:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[XS] Change in coreboot[main]: UPSTREAM: soc/mediatek/common: Fix eMMC clock
by Kiwi Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu. Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: UPSTREAM: soc/mediatek/common: Fix eMMC clock ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/a972f32a_009d2449?us… : PS1, Line 7: WIP: > Is this patch ready for review ? Done https://review.coreboot.org/c/coreboot/+/84298/comment/ea604c64_f56cf4cd?us… : PS1, Line 9: 2-3 MHz > MHz is used to describe the frequency not the interval. Done https://review.coreboot.org/c/coreboot/+/84298/comment/a27d24c0_ea0ec0a0?us… : PS1, Line 14: emerge-corsola coreboot > does it impact the boot time ? Impact can be ignored, because only very few commands in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 3 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 00:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: UPSTREAM: soc/mediatek/common: Fix eMMC clock
by Kiwi Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yu-Ping Wu. Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84298?usp=email to look at the new patch set (#3). Change subject: UPSTREAM: soc/mediatek/common: Fix eMMC clock ...................................................................... UPSTREAM: soc/mediatek/common: Fix eMMC clock Mediatek SOC start operating at eMMC clock around 2 MHz right after power-on. In JEDEC spec, this period is 400 kHz or less. BUG=b:356578805 TEST=emerge-corsola coreboot Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Tested-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com> Reviewed-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com> --- M src/soc/mediatek/common/msdc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 3 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: UPSTREAM: soc/mediatek/common: Fix eMMC clock
by Kiwi Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yu-Ping Wu. Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84298?usp=email to look at the new patch set (#2). Change subject: UPSTREAM: soc/mediatek/common: Fix eMMC clock ...................................................................... UPSTREAM: soc/mediatek/common: Fix eMMC clock Mediatek SOC start operating at eMMC clock 2-3 MHz right after power-on. In JEDEC spec, this period is 400 kHz or less. BUG=b:356578805 TEST=emerge-corsola coreboot Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Tested-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com> Reviewed-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com> --- M src/soc/mediatek/common/msdc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 2 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit September 2024