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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
......................................................................
Patch Set 9:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83979/comment/6aedecb7_42e228a3?us… :
PS7, Line 9: Adds
> Add
Done
https://review.coreboot.org/c/coreboot/+/83979/comment/424295b4_1b1ad44d?us… :
PS7, Line 10: 2
> The board has 4 USB ports on the back, and there's more USB ports on one of the headers
Done
File src/mainboard/hardkernel/odroid-h4/Kconfig:
https://review.coreboot.org/c/coreboot/+/83979/comment/8b9ad5dc_403d1b84?us… :
PS7, Line 28: string
> Type not needed
Done
File src/mainboard/hardkernel/odroid-h4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/f47975c5_da556188?us… :
PS7, Line 13: ite_reg_write(GPIO_DEV, 0x29, 0x01); // The value matches vendor firmware
: ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3
: ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup
: ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup
: ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function
> Are the comments accurate? I don't have a datasheet for this Super I/O
Gone
File src/mainboard/hardkernel/odroid-h4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83979/comment/61079cb1_c9847ccb?us… :
PS7, Line 5: register "pmc_gpe0_dw0" = "GPP_B"
: register "pmc_gpe0_dw1" = "GPP_D"
: register "pmc_gpe0_dw2" = "GPP_E"
> do those match what the vendor firmware does? CB:84213 has other values for that and at least the de […]
Adjusted accordingly, I have no idea where the original values came from. But I think none of the GPIOs are used for GPEs anyway.
https://review.coreboot.org/c/coreboot/+/83979/comment/49ac67e8_fa44844a?us… :
PS7, Line 36: device ref tcss_xhci on
> tcss xhci is unused; the pch xhci controller which is the one used is missing in the devicetree. […]
Done
File src/mainboard/hardkernel/odroid-h4/gpio.h:
PS7:
> i wonder if this is missing the vgpios; at least the other patch for adding the mainboard support ha […]
I'm not even sure what the VGPIOs do, nor why they would need to be configured. Board works fine as-is
File src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/3dce2b1e_6e6dcad3?us… :
PS7, Line 19: 0x52
> This is weird, but if it works (memory is detected and all capacity is found) then it's correct. […]
Done, works fine
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Angel Pons has uploaded a new patch set (#9) to the change originally created by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )
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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
......................................................................
mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+
board, but all of them use the same PCB (with different components).
Working:
- DDR5 SO-DIMM slot
- All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller
- UART to emit spam
- All video outputs (FSP GOP only lights up one output at a time)
- Booting to Linux on SATA SSD with SeaBIOS <current version>
- USB ports below the Ethernet connectors
- One USB port on the pin header
- Ethernet NICs
- S3 suspend/resume
- edk2 payload
Not working:
- Dual BIOS: flash chip switching mechanism is very sus
- PECI: undocumented protocol and undocumented Super I/O
Untested:
- Fan control: seems wonky because of onboard temp sensor
- Rest of Super I/O config: needs exorcism
- HDA codec: SPDIF is untestable
- M.2 slot (PCIe only, no SATA lanes)
- Windows (with edk2 payload)
- PCIe ASPM and friends
Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb
Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com>
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/hardkernel/Kconfig
A src/mainboard/hardkernel/Kconfig.name
A src/mainboard/hardkernel/odroid-h4/Kconfig
A src/mainboard/hardkernel/odroid-h4/Kconfig.name
A src/mainboard/hardkernel/odroid-h4/Makefile.mk
A src/mainboard/hardkernel/odroid-h4/board_info.txt
A src/mainboard/hardkernel/odroid-h4/bootblock.c
A src/mainboard/hardkernel/odroid-h4/data.vbt
A src/mainboard/hardkernel/odroid-h4/devicetree.cb
A src/mainboard/hardkernel/odroid-h4/dsdt.asl
A src/mainboard/hardkernel/odroid-h4/hda_verb.c
A src/mainboard/hardkernel/odroid-h4/mainboard.c
A src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c
13 files changed, 592 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83979/9
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84103/comment/1ce23334_17961d78?us… :
PS15, Line 110: fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : 0;
: if (fadt->gpe1_blk) {
> checking if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) is true and if so setting the 3 values wit […]
ref: https://review.coreboot.org/c/coreboot/+/84103/comment/50a29b42_1e50c3d7
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/07148cc0_caac8e17?us… :
PS11, Line 241: gpe0_mask
> Subrata, […]
Subrata,
I add an weak function to get the GPE1 event bits and change the gpe1 enable/disable to use its gpe1 masks instead of gpe0. note that pmc_disable_all_gpe and pmc_clear_all_gpe_status clear all EN and STS bits regardless of masks.
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 115 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/13
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 115 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/12
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