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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 24:
(4 comments)
Patchset:
PS24:
Thanks for accommodating the review feedback. Appreciate your dedication to understand the problem and go deep to resolve it.
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/aaab83ef_706ecd4b?us… :
PS14, Line 32: FSPM_MAX_NONTURBO_FREQ
> I have added comment with respect to this in the partnerbug Subrata - please take a look
Acknowledged
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/21e5da29_2a5fdb5d?us… :
PS19, Line 27: MAX_NONTURBO_PERFORMANCE
> > at which stage, you are seeing "CPU brown out" ? romstage or ramstage ? I assume you are seeing Bootfrequency=2?
> > -It happens in ramstage ( FspMultiPhaseSiInit)
>
> The BSP always boots at the HFM, or P1 frequency, which is aligned with the CPU soft strap. I don't believe we need to file a bug to align with this expectation. You can dump the perf MSR to check the current frequency and compare it to the HFM.
>
> Later, during the ramstage, when we enable Turbo and try to configure Turbo for all APs, we need to draw more power to switch to the supported turbo max.
>
> Since the battery is unable to draw enough power, the CPU browns out.
>
> The best solution to this situation would be to ensure that the BIOS is not enabling Turbo or the BSP frequency is limited to HFM/P1 max.
>
> What I am saying is that the boot frequency override only makes sense at the ramstage and not at the romstage because we are already booting using P1/HFM until the romstage. This UPD is used to prevent the BSP from switching to the Turbo frequency, knowing that the power envelope is not sufficient to keep Turbo enabled.
>
> > who is setting TurboModeDisable ? I assume croeboot can always override this.
> > - FSP - in function VOID SetBootFrequency (
> > IN SI_POLICY_PPI *SiPolicyPpi
> > )
> > If bootfreq is set 2 - I believe the boot will start in HPM and then switch to turbo mode (by looking at the code and logs) ..If this is not the expected behavior then we should follow it up a separate bug
>
> Please read my explanation above, I'm insisting this UPD is more like ramstage specific UPD rather getting used in romstage. Because turbo freq is what ideally we wish to avoid to switch for BSP unless we have ample supply.
I will move this discussion for FSP arch sync. Hence, marking it resolved here
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/a2982c6f_a96502cf?us… :
PS24, Line 77: 9
can you please move this into a Kconfig and keep a default value `9`. If any variant wish to override a better number, they can do that easily.
```
if (CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT)
soc_config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT;
```
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 24:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/1afeb40b_f0db7709?us… :
PS19, Line 57: * PL4 calculations - For USB C charger (Max Power):
> Got it - my experiments were with pl4 = 19 and pl4 = 23 for 65 watts adaptors and the observations w […]
subrata >>>if we know that OS can override the PL4 table dynamically and we only need to set a lower P4 when battery is not present. Then, it would be good to boot with a static configuration which is safest and generically applicable.
Adding logic to configure PL4 based on USB-PD capacity seems overdoing for BIOS.
Done - PL4 value is static = 9 watts (30W * 32%)
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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Ren Kuo, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins),
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/chip.h
4 files changed, 45 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/24
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Change subject: WIP: soc/mediatek/common: Fix eMMC clock
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/68e11d82_430a67e4?us… :
PS1, Line 7: WIP:
Is this patch ready for review ?
https://review.coreboot.org/c/coreboot/+/84298/comment/b3ef92d5_387cf824?us… :
PS1, Line 9: 2-3 MHz
MHz is used to describe the frequency not the interval.
https://review.coreboot.org/c/coreboot/+/84298/comment/1921583f_5fdcd39d?us… :
PS1, Line 14: emerge-corsola coreboot
does it impact the boot time ?
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Change subject: soc/mediatek: Remove redundant struct pad_func and PAD_* definitions
......................................................................
Patch Set 3:
(2 comments)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/84222/comment/87698039_af5c90ae?us… :
PS2, Line 59:
> `(struct pad_func)` to ensure the correct type. Same for the other macros below.
The compiler will raise `error: initializer element is not constant`.
https://review.coreboot.org/c/coreboot/+/84222/comment/221560ab_b819366c?us… :
PS2, Line 59: }
> Thanks. […]
Done
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Hello Hung-Te Lin, Xi Chen, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek: Remove redundant struct pad_func and PAD_* definitions
......................................................................
soc/mediatek: Remove redundant struct pad_func and PAD_* definitions
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch
also refactors the PAD_* micros by,
- Repurposing PAD_FUNC and dropping PAD_FUNC_SEL.
- Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit
initialization.
BUG=none
TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot
Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/common/flash_controller.c
M src/soc/mediatek/common/include/soc/flash_controller_common.h
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/common/include/soc/gpio_defs.h
M src/soc/mediatek/mt8183/i2c.c
M src/soc/mediatek/mt8183/spi.c
M src/soc/mediatek/mt8186/i2c.c
M src/soc/mediatek/mt8186/spi.c
M src/soc/mediatek/mt8188/i2c.c
M src/soc/mediatek/mt8188/spi.c
M src/soc/mediatek/mt8192/i2c.c
M src/soc/mediatek/mt8192/spi.c
M src/soc/mediatek/mt8195/i2c.c
M src/soc/mediatek/mt8195/pcie.c
M src/soc/mediatek/mt8195/spi.c
M src/soc/mediatek/mt8196/i2c.c
M src/soc/mediatek/mt8196/spi.c
18 files changed, 243 insertions(+), 335 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/84222/3
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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 14:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/6fb594a7_6e2dc077?us… :
PS11, Line 241: gpe0_mask
> Subrata,
> I add an weak function to get the GPE1 event bits and change the gpe1 enable/disable to use its gpe1 masks instead of gpe0. note that pmc_disable_all_gpe and pmc_clear_all_gpe_status clear all EN and STS bits regardless of masks.
Can you follow sample implementation as below, which might eliminate the need for weak implementation and also may qualify in future to move the GPE implementation inside yet another common code file (pmc_gpe1.c)
```
pmclib.h
----------------
#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask);
#else
static inline void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
{
/* Default implementation, nop. */
return;
}
#endif
pmclib.c
----------------
void pmc_enable_std_gpe(uint32_t mask)
{
pmc_enable_gpe0(GPE_STD, mask);
if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1))
return;
soc_pmc_enable_std_gpe1();
}
SoC Override when CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1=Y <---- this can now even move into a common code name pmc_gpe1.c when CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, but nothing must have now. we can keep SOC implementation for PTL
--------------
#define GPE1_EN(x) (0x1c + ((x) * 4))
static void soc_pmc_enable_gpe1_bits(int reg)
{
uint32_t gpe1_en = inl(ACPI_BASE_ADDRESS + reg);
gpe1_en |= 0xffffffff;
outl(gpe1_en, ACPI_BASE_ADDRESS + reg);
}
void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask_val)
{
uint32_t gpe0_bit_mask[GPE1_REG_MAX] = {
PME_B0_STS,
HOT_PLUG_STS,
PCI_EXP_STS
};
for (int i = 0; i < GPE1_REG_MAX; i++) {
if (gpe0_mask_val & gpe0_bit_mask[i] == gpe0_bit_mask[i])
soc_pmc_get_gpe1_bits(GPE1_EN(i));
}
}
```
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#17).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 123 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/17
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