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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
......................................................................
Patch Set 9:
(3 comments)
File src/mainboard/hardkernel/odroid-h4/Kconfig:
https://review.coreboot.org/c/coreboot/+/83979/comment/8fe10d6a_8674e59c?us… :
PS9, Line 10: select FSP_TYPE_IOT
> Is this needed? I remember the IoT FSP had some clock and power gating UPDs for PCIe RPs, is that it […]
There's no Client FSP for ADL-N at the time of writing.
https://review.coreboot.org/c/coreboot/+/83979/comment/d065d8d9_6e76438a?us… :
PS9, Line 18: select USE_LEGACY_8254_TIMER
> Do you want this in the board config, and as a select? I think it should be the user's/payload's cho […]
I don't remember why it was selected, but I can remove it.
File src/mainboard/hardkernel/odroid-h4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/90e091f9_8e1b9ad5?us… :
PS9, Line 13: ite_reg_write(GPIO_DEV, 0x26, 0xfb);
: ite_reg_write(GPIO_DEV, 0x29, 0x01);
: ite_reg_write(GPIO_DEV, 0x2c, 0x41);
: ite_reg_write(GPIO_DEV, 0x2d, 0x02);
: ite_reg_write(GPIO_DEV, 0xbc, 0xc0);
: ite_reg_write(GPIO_DEV, 0xbd, 0x03);
: ite_reg_write(GPIO_DEV, 0xc1, 0x0a);
: ite_reg_write(GPIO_DEV, 0xc8, 0x00);
: ite_reg_write(GPIO_DEV, 0xc9, 0x0a);
: ite_reg_write(GPIO_DEV, 0xda, 0xb0);
: ite_reg_write(GPIO_DEV, 0xdb, 0x44);
Not really. This sets up the Super I/O GPIOs, and the values come from vendor firmware. We don't have the datasheet for this Super I/O so I'm not sure what the values mean. I will expand the comment above, though:
> Set up Super I/O GPIOs, values come from vendor firmware
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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
......................................................................
Patch Set 9:
(3 comments)
File src/mainboard/hardkernel/odroid-h4/Kconfig:
https://review.coreboot.org/c/coreboot/+/83979/comment/bbec625b_3012a024?us… :
PS9, Line 10: select FSP_TYPE_IOT
Is this needed? I remember the IoT FSP had some clock and power gating UPDs for PCIe RPs, is that it here?
https://review.coreboot.org/c/coreboot/+/83979/comment/50080eaf_e9d7b8c4?us… :
PS9, Line 18: select USE_LEGACY_8254_TIMER
Do you want this in the board config, and as a select? I think it should be the user's/payload's choice
File src/mainboard/hardkernel/odroid-h4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/83979/comment/e408410b_b7bdffc2?us… :
PS9, Line 13: ite_reg_write(GPIO_DEV, 0x26, 0xfb);
: ite_reg_write(GPIO_DEV, 0x29, 0x01);
: ite_reg_write(GPIO_DEV, 0x2c, 0x41);
: ite_reg_write(GPIO_DEV, 0x2d, 0x02);
: ite_reg_write(GPIO_DEV, 0xbc, 0xc0);
: ite_reg_write(GPIO_DEV, 0xbd, 0x03);
: ite_reg_write(GPIO_DEV, 0xc1, 0x0a);
: ite_reg_write(GPIO_DEV, 0xc8, 0x00);
: ite_reg_write(GPIO_DEV, 0xc9, 0x0a);
: ite_reg_write(GPIO_DEV, 0xda, 0xb0);
: ite_reg_write(GPIO_DEV, 0xdb, 0x44);
Do we know what this does?
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Nico Huber has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/libgfxinit/+/67494?usp=email )
Change subject: gma pipe_setup: Update for TGL & ADL
......................................................................
Patch Set 36:
(1 comment)
Patchset:
PS36:
> Maaaaaybe I can use CB:83979 to test this patch train?
Sure, I think ADL-N is really just ADL-P without P-cores.
I also have some small ADL-P board (w/o coreboot) that I wanted to test gfx_test on.
But didn't get that far yet. TGL seems pretty much working right now with my latest
pushes but there are some regressions in the big CB:67801 sink. I'm currently trying
to untangle this in my spare time right now (again; originally it was a small patch
as the commit message suggests), but that branch is not ready for ADL testing.
Let me know if I should push that anyway.
I guess the ADL work is pretty much ready for the early sign-off live over eDP. But
the general boot-time graphics support looks more like it was left in a PoC state,
with the original, more comprehensive TGL work regressed. (That's all assuming that
we picked the right patches from the relation chain.)
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83708?usp=email )
Change subject: soc/intel/cml, pci_ids: Fix ID for Comet Lake-H GT2
......................................................................
soc/intel/cml, pci_ids: Fix ID for Comet Lake-H GT2
According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics
630" for the Coffee Lake processor family and has already been added to
the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2.
At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1],
which is missing in the file.
[1] https://web.archive.org/web/20240731152818/https://dgpu-docs.intel.com/devices/hardware-table.html
Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
---
M src/include/device/pci_ids.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin L Roth: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 54fe0c1..24799b8 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4193,7 +4193,7 @@
#define PCI_DID_INTEL_CML_GT2_H_2 0x9B42
#define PCI_DID_INTEL_CML_GT2_S_G0 0x9BC8
#define PCI_DID_INTEL_CML_GT2_S_P0 0x9BC5
-#define PCI_DID_INTEL_CML_GT2_H_R0 0x3E9B
+#define PCI_DID_INTEL_CML_GT2_H_R0 0x9BC2
#define PCI_DID_INTEL_CML_GT2_H_R1 0x9BC4
#define PCI_DID_INTEL_TGL_GT1 0x9A60
#define PCI_DID_INTEL_TGL_GT2_UY 0x9A49
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83872?usp=email )
Change subject: util/lint/lint-final-newlines: Supply dirs in row
......................................................................
util/lint/lint-final-newlines: Supply dirs in row
This just orders the EXCLUDED_DIRS directories in a row based manner,
since there are quite a few them now and it is arguably easier to read
and to add new directories if they are written in a row based fashion.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I802aece355bba4900e71824d802c4b2438726e84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
---
M util/lint/lint-extended-015-final-newlines
1 file changed, 11 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin L Roth: Looks good to me, approved
diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines
index 4ea4536..18ca75b 100755
--- a/util/lint/lint-extended-015-final-newlines
+++ b/util/lint/lint-extended-015-final-newlines
@@ -14,7 +14,17 @@
PIDS=""
INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc'
-EXCLUDED_DIRS='src/vendorcode/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/\|^util/goswid/vendor'
+EXCLUDED_DIRS="\
+src/vendorcode/\|\
+cbfstool/lzma/\|\
+cbfstool/lz4/\|\
+Documentation/\|\
+build/\|\
+3rdparty/\|\
+\.git/\|\
+coreboot-builds/\|\
+util/nvidia/cbootimage/\|\
+^util/goswid/vendor"
EXCLUDED_FILES='\.gif$\|\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$\|\.apcb$'
HAVE_FILE=$(command -v file 1>/dev/null 2>&1; echo $?)
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Change subject: amdfwtool: Add a unified function to add combo entries
......................................................................
Patch Set 4: Code-Review+2
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Change subject: amdfwtool: Add combo new layout for new family
......................................................................
Patch Set 9: Code-Review+2
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