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Change subject: edid.h: Increase EDID_ASCII_STRING_LENGTH to 14
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
The 13 here come from the EDID specification, we should not change it. The panels in src/drivers/mipi don't have real EDIDs, we're just reusing the data structure to have a common interface for display parameters. I think the correct fix here is to just truncate the MIPI panel names in whatever way makes sense to fit in 13 bytes (without terminating '\0').
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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
> can this patch and CB:84213 be combined somehow?
good idea. Since this patch lands the base patch for all H4 series, and CB:84213 is added for H4+ support, could rebase CB:84213 on top of this. Angel also did a thorough tests and updated those info per commit message.
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Change subject: mainboard/hardkernel: Add ODROID H4+ initial support
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/hardkernel/odroid_h4/gpio.c:
https://review.coreboot.org/c/coreboot/+/84213/comment/eb318bed_e59be967?us… :
PS2, Line 8: #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \
> shouldn't this go into one of the soc's gpio header files?
can be removed if rebased on top of CB:42914
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Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
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Patch Set 9:
(1 comment)
Patchset:
PS9:
can this patch and CB:84213 be combined somehow?
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Change subject: mainboard/hardkernel: Add ODROID H4+ initial support
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Patch Set 2:
(1 comment)
Patchset:
PS2:
can this patch and CB:83979 be combined somehow?
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 27:
(4 comments)
File src/mainboard/google/brox/Kconfig:
https://review.coreboot.org/c/coreboot/+/83752/comment/922aeb94_db8d3d17?us… :
PS27, Line 124: Select this if the variant has to boot for low battery, battery at critical threshold
: or when battery is disconnected physically. PL4 which is processor Instataneous Power
: or Absolute Peak Power controls the highest power draw from processor at any given
: instant of time within Pl1Tau duration. Hence PL4 acts as a fail safe mechanism to set an
: upper threshold limit for processor instantaneous power draw. For a 30W adapter, the
: maximum peak power is set at 9 watts which is 30W multiplied by 32 percent efficiency.
: This default pl4 value is set for 30W or any higher adapter rating such as 45W or 65W.
Select this if the variant has to boot even with low battery, critical battery threshold, or when the battery is physically disconnected. PL4, which stands for Processor Instantaneous Power or Absolute Peak Power, controls the highest power draw from the processor at any given moment within the Pl1Tau duration. Therefore, PL4 acts as a failsafe mechanism to set an upper threshold limit for the processor's instantaneous power draw. For a 30W adapter, the maximum peak power is set at 9 watts, which is 30W multiplied by 32% efficiency. This default pl4 value is set for 30W or any higher adapter rating, such as 45W or 65W.
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/e47e2212_52505f77?us… :
PS27, Line 16: FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
you can move this line inside `if` case in line 27
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/a6b638c3_e2ac8d30?us… :
PS27, Line 74: else
: soc_config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT;
please use braces as we have multi-line `if` case as well.
https://review.coreboot.org/c/coreboot/+/83752/comment/fd780543_3014e55f?us… :
PS27, Line 70: if (google_chromeec_is_battery_present_and_above_critical_threshold()) {
: if (soc_config->tdp_pl4 == 0)
: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power,
: MILLIWATTS_TO_WATTS);
: } else
: soc_config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT;
:
can we move this into a local function like `variant_pl4_override(soc_config)`
```
static void variant_pl4_override(const struct soc_power_limits_config *config)
{
if (google_chromeec_is_battery_present_and_above_critical_threshold()) {
if (config->tdp_pl4 == 0)
config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power, MILLIWATTS_TO_WATTS);
} else {
if (CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT)
config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT;
}
}
```
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Change subject: mb/google/brox: Set PCIE WLAN bluetooth companion device
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Patch Set 1: Code-Review+1
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Change subject: mb/google/brox/var/lotso: Update verb table
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84184/comment/b713cdd3_8ce29ee8?us… :
PS3, Line 7: Update verb table
:
Please be more specific next time. For example:
> Increase number of NID entries from 15 to 16
https://review.coreboot.org/c/coreboot/+/84184/comment/c22fe4f9_a8130b1e?us… :
PS3, Line 9: Correct the number of NID entries.
Why is the new value the correct one?
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