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Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/common: Fix eMMC clock
......................................................................
soc/mediatek/common: Fix eMMC clock
Mediatek SOC start operating at eMMC clock around 2 MHz
right after power-on.
In JEDEC spec, this period is 400 kHz or less.
BUG=b:356578805
TEST=emerge-corsola coreboot
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Tested-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com>
Reviewed-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com>
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/4
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Change subject: UPSTREAM: soc/mediatek/common: Fix eMMC clock
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/3620ad95_e8ff6d1e?us… :
PS3, Line 7: UPSTREAM:
remove
https://review.coreboot.org/c/coreboot/+/84298/comment/dc8e658a_be65de96?us… :
PS3, Line 9: Mediatek SOC start operating at eMMC clock around 2 MHz
: right after power-on.
: In JEDEC spec, this period is 400 kHz or less.
```
MediaTek SoC operates eMMC clock around 2 MHz right after power-on. In JEDEC spec, the operating clock should be 400 kHz or less.
```
Please wrap the text at 72 characters.
https://review.coreboot.org/c/coreboot/+/84298/comment/e9a3dedc_48b28991?us… :
PS3, Line 14: emerge-corsola coreboot
I don't think this is a proper test method.
https://review.coreboot.org/c/coreboot/+/84298/comment/822335c4_4cac224f?us… :
PS3, Line 19: Tested-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com>
: Reviewed-by: Konishi Yoshi <konishi_yoshi(a)fujitsu.corp-partner.google.com>
remove
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Change subject: soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routed
......................................................................
Patch Set 4:
This change is ready for review.
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Hello Johnny Lin,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84327?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp/gnr: Enable VMX by FSP
......................................................................
soc/intel/xeon_sp/gnr: Enable VMX by FSP
Configure FSP UPD VMX from Kconfig ENABLE_VMX.
Change-Id: I0c03f535b6f93761419657127e791c02e8ee4988
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/soc/intel/xeon_sp/gnr/cpu.c
M src/soc/intel/xeon_sp/gnr/romstage.c
2 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/84327/1
diff --git a/src/soc/intel/xeon_sp/gnr/cpu.c b/src/soc/intel/xeon_sp/gnr/cpu.c
index ebccb08..5805035 100644
--- a/src/soc/intel/xeon_sp/gnr/cpu.c
+++ b/src/soc/intel/xeon_sp/gnr/cpu.c
@@ -34,8 +34,9 @@
printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n",
__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
- /* Enable VMX */
- set_vmx_and_lock();
+ /* Only lock and let vmx enabled by FSP to avoid FSP always triggering power good reset
+ due to vmx configuration conflict */
+ set_feature_ctrl_lock();
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/soc/intel/xeon_sp/gnr/romstage.c b/src/soc/intel/xeon_sp/gnr/romstage.c
index e61471e..48d88aa 100644
--- a/src/soc/intel/xeon_sp/gnr/romstage.c
+++ b/src/soc/intel/xeon_sp/gnr/romstage.c
@@ -66,6 +66,11 @@
"FSP_BOOT_WITH_FULL_CONFIGURATION.\n");
}
+ if (CONFIG(ENABLE_VMX))
+ m_cfg->VmxEnable = 1;
+ else
+ m_cfg->VmxEnable = 0;
+
/* Board level settings */
mainboard_memory_init_params(mupd);
}
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Change subject: soc/intel/xeon_sp/gnr: Remove duplicated HPET table
......................................................................
soc/intel/xeon_sp/gnr: Remove duplicated HPET table
Both lpc.c and chip.c will create HPET table.
remove hpet_device_ops for avoiding create two HPET table.
Change-Id: I32628e98b5c1fac4b72ea3abf755b62847161bec
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/chip.c
M src/soc/intel/xeon_sp/gnr/chipset.cb
2 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84326/1
diff --git a/src/soc/intel/xeon_sp/gnr/chip.c b/src/soc/intel/xeon_sp/gnr/chip.c
index aa9b378..45a0173 100644
--- a/src/soc/intel/xeon_sp/gnr/chip.c
+++ b/src/soc/intel/xeon_sp/gnr/chip.c
@@ -9,12 +9,6 @@
#include "chip.h"
-struct device_operations hpet_device_ops = {
-#if CONFIG(HAVE_ACPI_TABLES)
- .write_acpi_tables = &acpi_write_hpet,
-#endif
-};
-
struct device_operations cpu_bus_ops = {
.init = mp_cpu_bus_init,
};
diff --git a/src/soc/intel/xeon_sp/gnr/chipset.cb b/src/soc/intel/xeon_sp/gnr/chipset.cb
index ef33eac..a27b1d7 100644
--- a/src/soc/intel/xeon_sp/gnr/chipset.cb
+++ b/src/soc/intel/xeon_sp/gnr/chipset.cb
@@ -16,6 +16,5 @@
device domain 0 on
device pci 00.0 mandatory end # MMAP/VT-d
device gpio 0 alias ibl_gpio_communities on end # GPIO
- device mmio 0xfed00000 on ops hpet_device_ops end # HPET
end
end
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Hello Jincheng Li,
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Change subject: acpi: Create MADT lapic entries according to current lapic mode
......................................................................
acpi: Create MADT lapic entries according to current lapic mode
Introduce a new function is_x2apic_mode() to tell current lapic
mode and create the lapic entries accordingly.
Expose is_x2apic_mode() from x86 to common
Change-Id: I197ceeabd8a789abcd72459493a63ea267af4a16
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/acpi/acpi_apic.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84324/1
diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c
index fe0459b..d64b6c1 100644
--- a/src/acpi/acpi_apic.c
+++ b/src/acpi/acpi_apic.c
@@ -3,9 +3,11 @@
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
+#include <assert.h>
#include <commonlib/sort.h>
#include <cpu/cpu.h>
#include <device/device.h>
+#include <cpu/x86/lapic.h>
static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
{
@@ -32,9 +34,11 @@
unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id)
{
- if (lapic_id <= ACPI_MADT_MAX_LAPIC_ID)
+ if (!is_x2apic_mode()) {
+ assert(lapic_id <= ACPI_MADT_MAX_LAPIC_ID);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index,
lapic_id);
+ }
else
current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index,
lapic_id);
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Hello Chen, Gang C, Jincheng Li,
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Change subject: arch/x86: Shadow ROM tables into EBDA
......................................................................
arch/x86: Shadow ROM tables into EBDA
For platforms without writable PAM-F segment support (e.g. some
simics virtual platforms), put ROM table pointers (e.g. ACPI/SMBIOS
low pointers) into EBDA.
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
Change-Id: I2aac74708279813f9a848044d470fdc980ea4305
---
M src/arch/x86/Kconfig
M src/arch/x86/tables.c
2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/84322/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index cc68f5c..d6434ae 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -439,4 +439,11 @@
default 0x400
help
The default value of EBDA size is 0x400.
+
+config SHADOW_ROM_TABLE_TO_EBDA
+ bool "Shadow ROM tables to EBDA"
+ default n
+ help
+ For platforms without writable PAM-F segment support. Put ROM table
+ pointers (e.g. ACPI/SMBIOS low pointers) into EBDA.
endif
diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index 2732638..e47f1bc 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -192,7 +192,12 @@
void arch_write_tables(uintptr_t coreboot_table)
{
size_t sz;
- unsigned long rom_table_end = 0xf0000;
+ unsigned long rom_table_end;
+
+ if (CONFIG(SHADOW_ROM_TABLE_TO_EBDA))
+ rom_table_end = CONFIG_DEFAULT_EBDA_SEGMENT << 4;
+ else
+ rom_table_end = 0xf0000;
/* This table must be between 0x0f0000 and 0x100000 */
if (CONFIG(GENERATE_PIRQ_TABLE))
@@ -224,4 +229,8 @@
const uintptr_t base = 0;
bootmem_add_range(base, forwarding_table - base, BM_MEM_TABLE);
+
+ /* Reserve Extend BIOS Data Area (EBDA) region explicitly */
+ bootmem_add_range((uintptr_t)CONFIG_DEFAULT_EBDA_SEGMENT << 4,
+ CONFIG_DEFAULT_EBDA_SIZE, BM_MEM_TABLE);
}
--
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