Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84316?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms
......................................................................
soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms
Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/84316/1
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 9ba04fa..0e3fd8f 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -268,7 +268,7 @@
// Add DRHD Hardware Unit
- if (is_dev_on_domain0(iommu)) {
+ if (!CONFIG(SOC_INTEL_COMMON_IBL_BASE) && is_dev_on_domain0(iommu)) {
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
"Register Base Address: 0x%x\n",
DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);
--
To view, visit https://review.coreboot.org/c/coreboot/+/84316?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5
Gerrit-Change-Number: 84316
Gerrit-PatchSet: 1
Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84315?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp: Report RCiEPs under DRHD
......................................................................
soc/intel/xeon_sp: Report RCiEPs under DRHD
In case of a PCH-less platform, all RCiEPs should be listed under
its specific DRHD
Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84315/1
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index baffdd0..9ba04fa 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -336,22 +336,22 @@
#endif
}
- // Add IOAT End Points (with memory resources. We don't report every End Point device.)
- if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) {
- struct device *dev = NULL;
- while ((dev = dev_find_all_devices_on_stack(socket, stack,
- XEONSP_VENDOR_MAX, XEONSP_DEVICE_MAX, dev)))
- /* This may also require a check for IORESOURCE_PREFETCH,
- * but that would not include the FPU (4942/0) */
- if ((dev->resource_list->flags &
- (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) ==
- (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) {
- const uint32_t b = dev->upstream->secondary;
- const uint32_t d = PCI_SLOT(dev->path.pci.devfn);
- const uint32_t f = PCI_FUNC(dev->path.pci.devfn);
- printk(BIOS_DEBUG, " [PCIE Endpoint Device] %s\n", dev_path(dev));
- current += acpi_create_dmar_ds_pci(current, b, d, f);
- }
+ struct device *dev = NULL;
+ while ((dev = dev_find_all_devices_on_stack(socket, stack,
+ XEONSP_VENDOR_MAX, XEONSP_DEVICE_MAX, dev))) {
+ const uint32_t b = dev->upstream->secondary;
+ const uint32_t d = PCI_SLOT(dev->path.pci.devfn);
+ const uint32_t f = PCI_FUNC(dev->path.pci.devfn);
+ struct device *upstream_dev = dev->upstream->dev;
+
+ if (is_pci_bridge(dev))
+ continue;
+
+ if (upstream_dev->path.type != DEVICE_PATH_DOMAIN)
+ continue;
+
+ printk(BIOS_DEBUG, " [PCIE Endpoint Device] %s\n", dev_path(dev));
+ current += acpi_create_dmar_ds_pci(current, b, d, f);
}
// Add HPET
--
To view, visit https://review.coreboot.org/c/coreboot/+/84315?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa
Gerrit-Change-Number: 84315
Gerrit-PatchSet: 1
Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84312?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 1152
......................................................................
soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 1152
GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge
MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered.
Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/84312/1
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index fae9d8d..85990cd 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -30,7 +30,7 @@
config MAX_CPUS
int
- default 255
+ default 1152
config PCR_BASE_ADDRESS
hex
--
To view, visit https://review.coreboot.org/c/coreboot/+/84312?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa
Gerrit-Change-Number: 84312
Gerrit-PatchSet: 1
Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84311?usp=email )
Change subject: soc/intel/xeon_sp: Support GNR PCIe root ports
......................................................................
soc/intel/xeon_sp: Support GNR PCIe root ports
Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.
Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/pcie_root_port.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/84311/1
diff --git a/src/soc/intel/xeon_sp/pcie_root_port.c b/src/soc/intel/xeon_sp/pcie_root_port.c
index fb9abde..6ecbcec 100644
--- a/src/soc/intel/xeon_sp/pcie_root_port.c
+++ b/src/soc/intel/xeon_sp/pcie_root_port.c
@@ -69,6 +69,14 @@
0x352c,
0x352d,
0x347a,
+ 0x0db0,
+ 0x0db1,
+ 0x0db2,
+ 0x0db3,
+ 0x0db6,
+ 0x0db7,
+ 0x0db8,
+ 0x0db9,
0
};
--
To view, visit https://review.coreboot.org/c/coreboot/+/84311?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Gerrit-Change-Number: 84311
Gerrit-PatchSet: 1
Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>