coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3
by Julia Kittlinger (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Felix Singer. Julia Kittlinger has posted comments on this change by Julia Kittlinger. ( https://review.coreboot.org/c/coreboot/+/84444?usp=email ) Change subject: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3 ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84444/comment/8b0133f6_c8eb2577?us… : PS1, Line 7: myself > When the git log is viewed in short mode, it's not visible who "myself" is. […] Done File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/84444/comment/bfb533da_7dbb4eb6?us… : PS1, Line 130: * > Remove the asterisk. That does not cover the whole subcontent. Done https://review.coreboot.org/c/coreboot/+/84444/comment/56b682da_8584b109?us… : PS1, Line 131: > We only use one blank line when the target is in the same group, e.g. the same vendor. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Gerrit-Change-Number: 84444 Gerrit-PatchSet: 2 Gerrit-Owner: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sat, 21 Sep 2024 00:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3
by Felix Singer (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Felix Singer, Julia Kittlinger. Felix Singer has posted comments on this change by Julia Kittlinger. ( https://review.coreboot.org/c/coreboot/+/84444?usp=email ) Change subject: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Oh, and it's very unusual that authors add a review score to their own patches. There are corner cases though, but they don't apply here. Please remove your own review score. -- To view, visit https://review.coreboot.org/c/coreboot/+/84444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Gerrit-Change-Number: 84444 Gerrit-PatchSet: 1 Gerrit-Owner: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Comment-Date: Sat, 21 Sep 2024 00:46:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as reviewer for ACER G43T-AM3
by Felix Singer (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Julia Kittlinger. Felix Singer has posted comments on this change by Julia Kittlinger. ( https://review.coreboot.org/c/coreboot/+/84444?usp=email ) Change subject: MAINTAINERS: Add myself as reviewer for ACER G43T-AM3 ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Patchset: PS1: A few things, but otherwise looks good. Thanks! Commit Message: https://review.coreboot.org/c/coreboot/+/84444/comment/18461818_dbe4ac94?us… : PS1, Line 7: myself When the git log is viewed in short mode, it's not visible who "myself" is. So please use your name here. File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/84444/comment/d88d105f_ba622ed8?us… : PS1, Line 130: * Remove the asterisk. That does not cover the whole subcontent. https://review.coreboot.org/c/coreboot/+/84444/comment/1de58133_5b593971?us… : PS1, Line 131: We only use one blank line when the target is in the same group, e.g. the same vendor. Please remove 2 lines. -- To view, visit https://review.coreboot.org/c/coreboot/+/84444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Gerrit-Change-Number: 84444 Gerrit-PatchSet: 1 Gerrit-Owner: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Comment-Date: Sat, 21 Sep 2024 00:42:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as reviewer for ACER G43T-AM3
by Julia Kittlinger (Code Review) 21 Sep '24

21 Sep '24

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as reviewer for ACER G43T-AM3
by Julia Kittlinger (Code Review) 21 Sep '24

21 Sep '24

Julia Kittlinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84444?usp=email ) Change subject: MAINTAINERS: Add myself as reviewer for ACER G43T-AM3 ...................................................................... MAINTAINERS: Add myself as reviewer for ACER G43T-AM3 Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Signed-off-by: Julia Kittlinger <julia.kittlinger(a)pm.me> --- M MAINTAINERS 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84444/1 diff --git a/MAINTAINERS b/MAINTAINERS index edf8561..71cfed2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -124,6 +124,13 @@ +ACER G43T-AM3 +R: Julia Kittlinger <julia.kittlinger(a)pm.me> +S: Orphan +F: src/mainboard/acer/g43t-am3/* + + + ACER MAINBOARDS S: Orphan F: src/mainboard/acer/ -- To view, visit https://review.coreboot.org/c/coreboot/+/84444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Gerrit-Change-Number: 84444 Gerrit-PatchSet: 1 Gerrit-Owner: Julia Kittlinger <julia.kittlinger(a)pm.me>

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[S] Change in coreboot[main]: util/cbfstool: Make sure to only compare PT_LOAD stages
by Julius Werner (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Arthur Heymans. Julius Werner has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84140?usp=email ) Change subject: util/cbfstool: Make sure to only compare PT_LOAD stages ...................................................................... Patch Set 2: (2 comments) File util/cbfstool/cbfs-mkstage.c: https://review.coreboot.org/c/coreboot/+/84140/comment/cdf20f6d_99fcfdf9?us… : PS2, Line 295: xip_ This function is currently only used for XIP parsing but I don't think it fundamentally only works for XIP stages? https://review.coreboot.org/c/coreboot/+/84140/comment/af791ea6_5cde26d6?us… : PS2, Line 317: if (!prev) What you do here works, but honestly I had to re-read it 3 times to understand what's going on. Updating prev at the top of the loop and relying on the fact that cur is not yet updated is not at all intuitive. How about, as an alternative, you rewrite the loop from here to say ``` if (prev && (prev->p_paddr + ... || ...)) { ...ERROR... } prev = cur; } ``` I feel like that would be a much more normal way to write the "keep track of previous pointer" pattern, and achieves the same goal of not counting the non-PT_LOAD entries. -- To view, visit https://review.coreboot.org/c/coreboot/+/84140?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I305b25032a3c4a9fdefc76cad77fafdb862a604c Gerrit-Change-Number: 84140 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 20 Sep 2024 23:35:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: efi: Set EFIAPI to 32-bit ABI for FSP1_1
by Felix Held (Code Review) 21 Sep '24

21 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84402?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: efi: Set EFIAPI to 32-bit ABI for FSP1_1 ...................................................................... efi: Set EFIAPI to 32-bit ABI for FSP1_1 Because PLATFORM_USES_FSP2_X86_32 default to false when PLATFORM_USES_FSP1_1, efi_datatype.h wrongly defines EFI as __attribute__((__ms_abi__)). TEST=When some code involved in the build of a platform using FSP 1.1 such as Google/CYAN includes efi_datatype.h, it does not hit the following error: '__ms_abi__' calling convention is not supported for this target Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5d Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84402 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/efi/efi_datatype.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index d4152af..a5e8ec3 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -13,7 +13,7 @@ * * Fortunately, EDK2 header allows to override EFIAPI. */ -#if CONFIG(PLATFORM_USES_FSP2_X86_32) +#if CONFIG(PLATFORM_USES_FSP1_1) || CONFIG(PLATFORM_USES_FSP2_X86_32) #define EFIAPI __attribute__((regparm(0))) #else #define EFIAPI __attribute__((__ms_abi__)) -- To view, visit https://review.coreboot.org/c/coreboot/+/84402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5d Gerrit-Change-Number: 84402 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/intel: Correct number of jacks in hda_verb.c
by Felix Held (Code Review) 21 Sep '24

21 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84424?usp=email ) Change subject: mb/intel: Correct number of jacks in hda_verb.c ...................................................................... mb/intel: Correct number of jacks in hda_verb.c This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c M src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c M src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h M src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c index 9c1759d..d41d8df 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c @@ -47,7 +47,7 @@ /* ALC700 */ 0x10EC0700, 0xFFFFFFFF, - 0x00000015, + 22, /* * HDA Codec Subsystem ID Verb-table diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c index 9c1759d..d41d8df 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c @@ -47,7 +47,7 @@ /* ALC700 */ 0x10EC0700, 0xFFFFFFFF, - 0x00000015, + 22, /* * HDA Codec Subsystem ID Verb-table diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c index 01012dd..3adda00 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/hda_verb.c @@ -6,7 +6,7 @@ /* ALC 700 */ 0x10EC0700, 0xFFFFFFFF, - 0x00000023, + 161, AZALIA_SUBVENDOR(0, 0x10EC10F2), AZALIA_PIN_CFG(0, 0x01, 0x00000000), diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h index 10c8a8f..52afaa9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h @@ -32,7 +32,7 @@ /* ALC 298 */ 0x10EC0298, 0x00000000, - 0x00000023, + 40, AZALIA_SUBVENDOR(0, 0x10EC109C), AZALIA_PIN_CFG(0, 0x01, 0x00000000), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h index 6915638..4c3074b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h @@ -32,7 +32,7 @@ /* ALC 286 */ 0x10EC0286, 0x00000000, - 0x00000023, + 38, AZALIA_SUBVENDOR(0, 0x10EC108E), AZALIA_PIN_CFG(0, 0x01, 0x00000000), diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h index 493b187..38f56f0 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h @@ -32,7 +32,7 @@ /* ALC 286 */ 0x10EC0286, 0x00000000, - 0x00000023, + 38, AZALIA_SUBVENDOR(0, 0x10EC1092), AZALIA_PIN_CFG(0, 0x01, 0x00000000), -- To view, visit https://review.coreboot.org/c/coreboot/+/84424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a Gerrit-Change-Number: 84424 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array, 2nd try
by Julius Werner (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Angel Pons, Arthur Heymans, Elyes Haouas, Felix Held, Nico Huber. Julius Werner has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array, 2nd try ...................................................................... Patch Set 3: (3 comments) File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/84059/comment/91ecca98_9c02fbc6?us… : PS1, Line 317: chunk_len = MIN(MAX_FLASH_CMD_DATA_SIZE, chunk_len); > Seems fine to me. The caller of spi_flash_cmd_write_page_program(), and […] Why is this line still necessary when we've already checked that no page_size can be larger than 256? If you're worried that this might change in the future, it would be nice if we could have a compile time check instead. Maybe we can wrap all spi_flash_vendor_info struct definitions in a macro that adds a _Static_assert() for the page_size_shift? File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/84059/comment/8c42650c_32d7b0e1?us… : PS3, Line 136: /* Put the buffer in .bss to not put strain on the stack (it's limited in SMM) */ Too limited for 256 bytes? Maybe it's worth adding a STATIC_IN_SMM macro to not eat the extra stage size everywhere else (some pre-RAM stages on some platforms are also counting the bytes...)? https://review.coreboot.org/c/coreboot/+/84059/comment/8714cd78_73fd19ff?us… : PS3, Line 140: return -1; assert()? -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 20 Sep 2024 23:22:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Felix Held (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik. Felix Held has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 28: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/e7642486_12f3ca1d?us… : PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */ : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a) : { : return NULL; : } : : /* disable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask) : { : } : : /* enable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask) : { : } > Felix, build issue fixed? the point i tried to make was that there's no need to have some weak (or regular) implementation of those 3 functions when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 isn't selected, since those function calls will become unreachable when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 isn't selected, so the compiler will just optimize out the calls and so the linker won't run into a problem due to those not bring implemented in that case. the current implementation has the advantage over the one with the weak function, that the case where SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is selected, but the 3 functions aren't implemented in the soc code will be caught in the build process. i'll just mark this one as resolved; don't want to cause too much delay for you -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 28 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 20 Sep 2024 23:21:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit September 2024