coreboot-gerrit September 2024

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Simplify FSP global reset definition
by Nico Huber (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Jérémy Compostella. Nico Huber has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email ) Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: A pity to see a good patch wasted. Instead of arguing how to handle FSP minutiae inside coreboot, I'd like to suggest an alternative: Encapsulation. Just don't even try to handle FSP ABI issues all over coreboot. If we'd encapsulate the ABI instead, we would only need a mapping from FSP ABI to coreboot. In this particular example this could be a proper, abstract `enum` for the reset type, where bits and values don't matter. Forcing us to always perform a conversion right after calling into FSP would also force us to check for unknown values right away (fsp_die_...) and then none of the coreboot internal code would have to preserve bit patterns of an alien ABI. I believe we could all have an easier job and a better time this way. Reading through the discussion here, I wondered: How can we expect to figure out what is right for coreboot when 80% of the discussion is referencing FSP specs? Some things don't mix well. Encapsulation would allow to discuss them separately, hopefully leading to nicer, simpler discussions. In the general case this could mean to forbid any `*fsp*` and `*efi*` in src/soc/intel/, also to forbid any #include of such headers. About everywhere where I've seen such includes, sooner or later there was trouble for a new platform. Probably because FSP/EFI is still a fork- per-platform endeavor while coreboot is not. Mixing these too without encapsulation is just asking for trouble. File src/soc/intel/common/fsp_reset.c: https://review.coreboot.org/c/coreboot/+/84356/comment/d2253894_250953e4?us… : PS11, Line 35: CONFIG_FSP_STATUS_GLOBAL_RESET > > > The updated spec recommends removing the need for the 32-bit hardcoded macros. > > > > Unfair as it does not. FSP 2.0 stated the use of highest bit and provided for the values for 32-bit only because FSP 2.0 is limited to 32-bits. > > If that's the case, why did Intel publish the reset type hardcoded macro between 0x40000001-0x40000008 in the FSP 2.3 spec? Why didn't they follow the same calculation they introduced in FSP 2.0 through FSP 2.3 for FSP 2.4? Subrata, what you reference is just a listing. A listing that tells you what values were chosen, not why. Jeremy has explained multiple times that they *did* use the same calculation (as the spec states in the paragraphs right before the listing). So it's completely futile to ask why they didn't. If you don't have the time to fully follow the spec, that's ok, but then you shouldn't argue. -- To view, visit https://review.coreboot.org/c/coreboot/+/84356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Gerrit-Change-Number: 84356 Gerrit-PatchSet: 12 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sat, 21 Sep 2024 13:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD
by Paul Menzel (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Paul Menzel has posted comments on this change by Curtis Chen. ( https://review.coreboot.org/c/coreboot/+/84452?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84452/comment/bb0c5cc9_b5b7e0f4?us… : PS1, Line 12: TEST=Deku can enter into S0iX. Please document the commands to check it. https://review.coreboot.org/c/coreboot/+/84452/comment/10978cee_afe585ff?us… : PS1, Line 13: If you can share the SSD model, that’d be great too. -- To view, visit https://review.coreboot.org/c/coreboot/+/84452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Gerrit-Change-Number: 84452 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 21 Sep 2024 13:07:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3
by Paul Menzel (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Julia Kittlinger. Paul Menzel has posted comments on this change by Julia Kittlinger. ( https://review.coreboot.org/c/coreboot/+/84444?usp=email ) Change subject: MAINTAINERS: Add Julia Kittlinger as reviewer for ACER G43T-AM3 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I389934afcc533702078fc5533736f5e4a98cd553 Gerrit-Change-Number: 84444 Gerrit-PatchSet: 2 Gerrit-Owner: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Comment-Date: Sat, 21 Sep 2024 13:05:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD
by Curtis Chen (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Curtis Chen has posted comments on this change by Curtis Chen. ( https://review.coreboot.org/c/coreboot/+/84452?usp=email ) Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > > Yes, it could solve that issue. Already edit comment. […] Yes,they are the same changes for similar causes. Should we enable for Karis together,too? Or enable it separately and please Karis ODM do some verification? -- To view, visit https://review.coreboot.org/c/coreboot/+/84452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Gerrit-Change-Number: 84452 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 21 Sep 2024 10:03:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Curtis Chen <curtis.chen(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Add missing usb port aliases
by Maxim (Code Review) 21 Sep '24

21 Sep '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84442?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cannonlake: Add missing usb port aliases ...................................................................... soc/intel/cannonlake: Add missing usb port aliases FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2]. [1] src/soc/intel/cannonlake/chip.h [2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/cannonlake/chipset_pch_h.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84442/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84442?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9 Gerrit-Change-Number: 84442 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD
by Subrata Banik (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Curtis Chen, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change by Curtis Chen. ( https://review.coreboot.org/c/coreboot/+/84452?usp=email ) Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > Yes, it could solve that issue. Already edit comment. thanks Curtis for adding test lines. Looks like the same changes already existed for Rex0 and Screebo but missed over Ovis/Deku/Karis hence, we might have experienced this issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/84452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Gerrit-Change-Number: 84452 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 21 Sep 2024 09:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Curtis Chen <curtis.chen(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD
by Curtis Chen (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Curtis Chen has posted comments on this change by Curtis Chen. ( https://review.coreboot.org/c/coreboot/+/84452?usp=email ) Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Do you if this is the reason for Phison SSD was not entering S0ix ? Yes, it could solve that issue. Already edit comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/84452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Gerrit-Change-Number: 84452 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 21 Sep 2024 08:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Enable RTD3 for SSD
by Curtis Chen (Code Review) 21 Sep '24

21 Sep '24

Attention is currently required from: Curtis Chen, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84452?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/deku: Enable RTD3 for SSD ...................................................................... mb/google/rex/var/deku: Enable RTD3 for SSD Deku S0ix is blocked by SSD. Enable RTD3 for SSD to unblock S0ix. BUG=361011799 TEST=Deku can enter into S0iX. suspend_stress_test w/o this CL (with Phison SSD) ``` Suspend failed, s0ix count did not increment from 19182060 Substate Residency S0i2.0 0 S0i2.1 0 S0i2.2 0 And PC10 residency is only 60% (by SoCWatch) ``` suspend_stress_test w/ this CL (with Phison SSD) ``` Substate Residency S0i2.0 0 S0i2.1 19186 S0i2.2 3389654 And PC10 residency is ~90% (by SoCWatch) Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84452/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649 Gerrit-Change-Number: 84452 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Update Flash Map layout
by Subrata Banik (Code Review) 21 Sep '24

21 Sep '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84453?usp=email ) Change subject: mb/google/fatcat: Update Flash Map layout ...................................................................... mb/google/fatcat: Update Flash Map layout This patch updates the fatcat flash map layout to accommodate the growth in Panther Lake IFWI blobs over Meteor Lake. Release FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 4MB -> 3MB Debug FMD: SI_ALL: 8MB -> 9MB SI_BIOS: 24MB -> 23MB RW_UNUSED: 3MB -> 2MB TEST=Able to build google/fatcat inside chroot. Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd M src/mainboard/google/fatcat/chromeos.fmd 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84453/1 diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd index 5b20f00..f34e495 100644 --- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -1,9 +1,9 @@ FLASH 32M { - SI_ALL 8M { + SI_ALL 9M { SI_DESC 16K SI_ME } - SI_BIOS 24M { + SI_BIOS 23M { RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) @@ -32,7 +32,7 @@ RW_FWID_B 64 } RW_LEGACY(CBFS) 1M - RW_UNUSED 3M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index 77f5555..61dd8cc 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -1,9 +1,9 @@ FLASH 32M { - SI_ALL 8M { + SI_ALL 9M { SI_DESC 16K SI_ME } - SI_BIOS 24M { + SI_BIOS 23M { RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) @@ -32,7 +32,7 @@ RW_FWID_B 64 } RW_LEGACY(CBFS) 1M - RW_UNUSED 4M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { -- To view, visit https://review.coreboot.org/c/coreboot/+/84453?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d Gerrit-Change-Number: 84453 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: xcompile: Disable unterminated-string-initialization warning
by Elyes Haouas (Code Review) 21 Sep '24

21 Sep '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84417?usp=email ) Change subject: xcompile: Disable unterminated-string-initialization warning ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icca87e333daf240b8dbc23c71863500294a37e74 Gerrit-Change-Number: 84417 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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