coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
by Kiwi Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Mengqi Zhang, Paul Menzel, Yu-Ping Wu. Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/3d83f7fa_145a7688?us… : PS9, Line 7: Fix eMMC clock > I meant `Reduce eMMC clock frequency to 400 kHz` Done https://review.coreboot.org/c/coreboot/+/84298/comment/71ba5440_cdf6334a?us… : PS9, Line 9: Mediatek SOC starts > MediaTek SoCs start Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 10 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 09:57:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
by Kiwi Liu (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Kiwi Liu, Mengqi Zhang, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84298?usp=email to look at the new patch set (#10). Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz ...................................................................... soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz Mediatek SOCs start operating at eMMC clock around 2 MHz right after power-on. In JEDEC spec, eMMC clock needs under 400 kHz. BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/msdc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 10 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: Makefile.mk: Add c-ccopts to LTO linking
by Arthur Heymans (Code Review) 12 Sep '24

12 Sep '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84337?usp=email ) Change subject: Makefile.mk: Add c-ccopts to LTO linking ...................................................................... Makefile.mk: Add c-ccopts to LTO linking arm adds some extra cflags via ccopts lie '-march='. Those are also necessary when linking with LTO. Change-Id: Ib1d890d4b4a3b812cb2969cbfa8bec77c3b6e0dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84337/1 diff --git a/Makefile.mk b/Makefile.mk index 5b48ca5..9a9aef42 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1329,7 +1329,7 @@ ifeq ($(CONFIG_LTO),y) $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(CC_$(1)) $$(CPPFLAGS_$(1)) $$(CFLAGS_$(1)) $$(LDFLAGS_$(1):%=-Wl,%) $(LTO_LINK_CFLAGS) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1):%=-Wl,%) -Wl,--whole-archive -Wl,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE)) + $$(CC_$(1)) $$(CPPFLAGS_$(1)) $$(CFLAGS_$(1)) $$(LDFLAGS_$(1):%=-Wl,%) $(LTO_LINK_CFLAGS) $$($(1)-c-ccopts) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1):%=-Wl,%) -Wl,--whole-archive -Wl,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE)) else $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/84337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1d890d4b4a3b812cb2969cbfa8bec77c3b6e0dc Gerrit-Change-Number: 84337 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: [TEST]Kconfig: Build all targets with LTO
by Arthur Heymans (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84033?usp=email to look at the new patch set (#37). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: [TEST]Kconfig: Build all targets with LTO ...................................................................... [TEST]Kconfig: Build all targets with LTO Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84033/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/84033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Gerrit-Change-Number: 84033 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: util/autoport: Add function to create empty files
by Nico Huber (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Angel Pons, Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84329?usp=email ) Change subject: util/autoport: Add function to create empty files ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I409a6d90d671258e318c26e34a35c238d6fd28c1 Gerrit-Change-Number: 84329 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 09:16:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/*/gpio: Remove local macros for bidirectional GPIO
by Maxim (Code Review) 12 Sep '24

12 Sep '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84336?usp=email ) Change subject: mb/*/gpio: Remove local macros for bidirectional GPIO ...................................................................... mb/*/gpio: Remove local macros for bidirectional GPIO These definitions are no longer necessary, since macros from intel/common are used in the configuration [1]. [1] CB:42914 Change-Id: I0a6061aa562ea98c1bcffd86adac9aea28d7766b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/51nb/x210/gpio.h M src/mainboard/aoostar/wtr_r1/gpio.h M src/mainboard/kontron/mal10/include/carrier/gpio.h M src/mainboard/protectli/vault_adl_p/gpio.c M src/mainboard/protectli/vault_ehl/gpio.h M src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h 6 files changed, 0 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/84336/1 diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index df12f5b..bb90b05 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -5,18 +5,6 @@ #include <soc/gpio.h> -/* - * Bidirectional GPIO port when both RX and TX buffer is enabled - * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h - */ -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - #ifndef __ACPI__ /* Pad configuration in ramstage. */ diff --git a/src/mainboard/aoostar/wtr_r1/gpio.h b/src/mainboard/aoostar/wtr_r1/gpio.h index 067b9ce..5317785 100644 --- a/src/mainboard/aoostar/wtr_r1/gpio.h +++ b/src/mainboard/aoostar/wtr_r1/gpio.h @@ -5,14 +5,6 @@ #include <gpio.h> -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/kontron/mal10/include/carrier/gpio.h b/src/mainboard/kontron/mal10/include/carrier/gpio.h index 9466b24..b771d82 100644 --- a/src/mainboard/kontron/mal10/include/carrier/gpio.h +++ b/src/mainboard/kontron/mal10/include/carrier/gpio.h @@ -5,27 +5,6 @@ #include <gpio.h> -/* - * Bidirectional GPIO port when both RX and TX buffer is enabled - * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h - */ -#ifndef PAD_CFG_GPIO_BIDIRECT_IOS -#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -#endif - -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - void carrier_gpio_configure(void); #endif /* CARRIER_GPIO_H */ diff --git a/src/mainboard/protectli/vault_adl_p/gpio.c b/src/mainboard/protectli/vault_adl_p/gpio.c index 1e65f03..212d439 100644 --- a/src/mainboard/protectli/vault_adl_p/gpio.c +++ b/src/mainboard/protectli/vault_adl_p/gpio.c @@ -4,14 +4,6 @@ #include "gpio.h" -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/protectli/vault_ehl/gpio.h b/src/mainboard/protectli/vault_ehl/gpio.h index 2f1c2ec..7eac656 100644 --- a/src/mainboard/protectli/vault_ehl/gpio.h +++ b/src/mainboard/protectli/vault_ehl/gpio.h @@ -5,14 +5,6 @@ #include <gpio.h> -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - /* PAD configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h index 4f98432..654dbdd 100644 --- a/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h @@ -5,18 +5,6 @@ #include <soc/gpio.h> -/* - * Bidirectional GPIO port when both RX and TX buffer is enabled - * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h - */ -#ifndef PAD_CFG_GPIO_BIDIRECT -#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(NO_DISABLE) | val, \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#endif - #ifndef __ACPI__ /* Pad configuration in ramstage. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a6061aa562ea98c1bcffd86adac9aea28d7766b Gerrit-Change-Number: 84336 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio
by Jian Tong (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Kun Liu, Paul Menzel. Jian Tong has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84254?usp=email ) Change subject: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Gerrit-Change-Number: 84254 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 08:40:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: use CONFIG_SMM_TSEG_SIZE
by Name of user not set (Code Review) 12 Sep '24

12 Sep '24

yuchi.chen(a)intel.com has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84334?usp=email ) Change subject: use CONFIG_SMM_TSEG_SIZE ...................................................................... Abandoned Pushed incorrectly, -- To view, visit https://review.coreboot.org/c/coreboot/+/84334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic489ebd871135bd72714b59fc1b4fed2f38e9c52 Gerrit-Change-Number: 84334 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: use CONFIG_SMM_TSEG_SIZE
by Name of user not set (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Paul Menzel. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84334?usp=email ) Change subject: use CONFIG_SMM_TSEG_SIZE ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84334/comment/031da02a_1b4208c3?us… : PS1, Line 7: use CONFIG_SMM_TSEG_SIZE > Please elaborate. Sorry I pushed incorrectly. -- To view, visit https://review.coreboot.org/c/coreboot/+/84334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic489ebd871135bd72714b59fc1b4fed2f38e9c52 Gerrit-Change-Number: 84334 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Sep 2024 08:21:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: lib: Compile memcpy and memset without LTO
by Arthur Heymans (Code Review) 12 Sep '24

12 Sep '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84335?usp=email ) Change subject: lib: Compile memcpy and memset without LTO ...................................................................... lib: Compile memcpy and memset without LTO GCC + LTO gets confused about this symbol not being present if compiled with LTO. Change-Id: Ieecd198932545d1ac2bbe0354183519c544ff971 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/Makefile.mk 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84335/1 diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index 40df2b8..aa7e3b9 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -34,6 +34,10 @@ # Must reset CCACHE_EXTRAFILES or make applies it transitively to dependencies. $(objcbfs)/bootblock.lz4: CCACHE_EXTRAFILES= +TARGETS := decompressor bootblock verstage romstage ramstage +$(foreach target,$(TARGETS),$(eval $(call src-to-obj,$(target),$(dir)/memcpy.c): CFLAGS_$(target) += -fno-lto)) +$(foreach target,$(TARGETS),$(eval $(call src-to-obj,$(target),$(dir)/memset.c): CFLAGS_$(target) += -fno-lto)) + decompressor-y += delay.c decompressor-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c decompressor-y += memchr.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieecd198932545d1ac2bbe0354183519c544ff971 Gerrit-Change-Number: 84335 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit September 2024