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Change subject: mb/google/nissa/var/riven: enable WIFI SAR
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/riven/variant.c:
https://review.coreboot.org/c/coreboot/+/84339/comment/8e9a982c_5c70da43?us… :
PS3, Line 10: if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_CNVI)) &&
> Suggest use fw_config_get_field to get the value and combine the value. Code should like this: […]
Good idea. Thanks.
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I'd like you to reexamine a change. Please visit
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Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/riven: enable WIFI SAR
......................................................................
mb/google/nissa/var/riven: enable WIFI SAR
According to the CL:chrome-internal:7651905,
Riven will use the fw_config to separate SAR setting.
CNVI + ID_0 --> wifi_sar_0.hex for WIFI6
PCIE + ID_1 --> wifi_sar_9.hex for WIFI7
BUG=b:366060274
TEST=build, enabled iwlwifi debug, and check dmesg
Cq-Depend: chrome-internal:7651905
Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/riven/overridetree.cb
M src/mainboard/google/brya/variants/riven/variant.c
3 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/84339/4
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Change subject: mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch
......................................................................
mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch
This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on EC console,"tabletmode" command shows "tablet mode".
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---
M src/mainboard/google/brya/variants/trulo/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/84351/3
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Change subject: mb/google/brox: Drop redundant entries of crashlog config
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/mt6366: Work around GCC LTO build
......................................................................
Patch Set 8:
(1 comment)
File src/soc/mediatek/mt8186/mt6366.c:
https://review.coreboot.org/c/coreboot/+/84208/comment/4f27016a_4644548c?us… :
PS8, Line 10: #define NO_BUILDTIME_ASSERT
> just because one assert statement in a file had this issue the other statements in that file are somehow more likely to also have it
Well, that's exactly the argument I made in my previous comment. I still think this statement is true, at least for this file. By "robust" I meant a workaround solution which will continue to work despite future changes of other code (until GCC fixes the bug). Therefore I actually prefer PS5 the most (PS5 > per-file > per-statement).
Consider the situation where someone adds a new regulator type for mt6366, which breaks some of the existing `assert()` calls in this file. They probably wouldn't notice that until uploading the patch and then seeing the Jenkins build failure. Then, they will see the error message, probably spend some time trying to fix the problem, and then eventually figure out they'd need to just change those calls to `assertX()`. My question is, why not changing all of them to `assertX()` *right now*, so that all of these potential hassles could be avoided?
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Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Hello Intel Team,
Can You please help to take a look into Crashlog error in JSL. Wondering if you have ever tested crashlog on JSL devices ?
File src/mainboard/google/dedede/Kconfig:
https://review.coreboot.org/c/coreboot/+/84359/comment/d40f9019_27a3d9a4?us… :
PS1, Line 39: select SOC_INTEL_CRASHLOG
> > to the problem that you faced while booting windows/linux on jsl Chromebook.
>
> actually, it seems to have nothing to do with OS or even payload; crashlog is just broken under JSL with upstream coreboot:
>
> [DEBUG] cmd_reg from pmc_make_ipc_cmd 1052838
> [ERROR] Null dereference at eip: 0x76ac8512
> [ERROR] Null dereference at eip: 0x76ac85ea
> [ERROR] Null dereference at eip: 0x76ac610c
> [DEBUG] PMC crashlog size in legacy mode = 0xd00
> [DEBUG] Read ID for Telemetry: 0x0 differs from expected: 0x23
> [ERROR] CPU crashlog capability not found.
> [DEBUG] PMC crashLog size in legacy mode : 0xD00
> [DEBUG] Invalid data 0x0 at offset 0x1300 from addr 0xfe010000 of PMC SRAM.
> [DEBUG] legacy mode PMC crashlog size adjusted to: 0x0
> [DEBUG] m_cpu_crashLog_size : 0x0 bytes
> [DEBUG] Skipping CPU crashLog collection. Data not present.
>
> unless this is expected behavior
CB:83884 tries to enable crashlog for JSL. I will talk to Intel team if they can take a look into it.
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