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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/fe874883_1634abd7?us… :
PS14, Line 32: FSPM_MAX_NONTURBO_FREQ
> can you please check what is the CPU debug soft-strap configuration? are you not booting by default […]
Last time I enquired PnP team they mentioned that P1 frequency and Boot frequency are different .
I dont have expertise on this - I will find out and get back to you.
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 14:
(3 comments)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/3d426403_824dffa1?us… :
PS14, Line 27: /* Sets the boot frequency starting from reset vector:
align w/ one more tab ?
https://review.coreboot.org/c/coreboot/+/83752/comment/0ec8d54a_5afe7239?us… :
PS14, Line 32: FSPM_MAX_NONTURBO_FREQ
can you please check what is the CPU debug soft-strap configuration? are you not booting by default using HFM (aka non-turbo max freq)? if not then why?
Ideally you should be always booting using HFM freq and only fall back (override the BootFrequency UPD) if battery is critically low. As you have experience that low-battery case is rare hence, make sense always boot using HFM and only fallback when we are in critical battery scenario. In such special case, system will hit a reset from FSP-M and then be able to override the CPU strap (to non-HFM freq). Because this override of BootFrequency is not sticky and will reset when we issue a cold/global reset.
I also hope that CSE sync is not at ramstage for Brox and happening before FSP-M at romstage, otherwise, we will experience few time additional resets due to overriding BootFrequency UPD.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/73965f2a_62a1c8ba?us… :
PS8, Line 365: BootFrequency
> In CPU soft strap I can see only processor boot at p1 frequency which is set as yes
that means, at reset BSP is always at non-Turbo max aka HFM freq
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 14:
(2 comments)
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/103147b8_439072cc?us… :
PS11, Line 15: #define SET_PSYSPL2(e, w) ((e) * (w) / 100)
> I am not sure about this - I wanted to first have a proven solution for Brox and then take it to oth […]
We only have lotso board - I can test it there
but other variants like greenbayupoc and Jubilant - I will not be able to test
https://review.coreboot.org/c/coreboot/+/83752/comment/7ee13b0f_57c80b97?us… :
PS11, Line 87: &volts_mv);
> will do
Done
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brox/variants/brox/ramstage.c
4 files changed, 85 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/14
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/romstage/fsp_params.c
5 files changed, 85 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/13
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Attention is currently required from: Arthur Heymans.
Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84013?usp=email )
Change subject: libpayload: Fix x86 output arch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> I may miss it, but I don't even see us preprocessing this file? […]
Actually, we do. I'm just getting the weirdest output (a lot of #define).
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Gerrit-Comment-Date: Mon, 26 Aug 2024 16:25:38 +0000
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