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Change subject: mb/google/brya/var/nova: Add scaler I2C configuration
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84091/comment/fa1bd2bb_dd92db2f?us… :
PS3, Line 7: Add scaler I2C configuration
Maybe: Configure scaler I2C GPIOs
https://review.coreboot.org/c/coreboot/+/84091/comment/07a90102_912b1053?us… :
PS3, Line 9: pins(PCH_I2C_SCALER_SDA/SDL)
Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/84091/comment/326852ff_dbed284a?us… :
PS3, Line 10:
Please document the source like the schematics.
https://review.coreboot.org/c/coreboot/+/84091/comment/ecae660c_60c3fe30?us… :
PS3, Line 12: TEST=emerge-constitution coreboot chromeos-bootimage
How can your change be verified?
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Change subject: Documentation/acronyms.md: Add some acronyms
......................................................................
Patch Set 1:
(1 comment)
File Documentation/acronyms.md:
https://review.coreboot.org/c/coreboot/+/83847/comment/c764f732_dea23c5c?us… :
PS1, Line 999: * STG - System-Top-Group apparently a term for grouping subsystems in an SOC together? TODO
is that TODO in there intended? i'd guess not
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Change subject: mb/lattepanda: Add support for LattePanda Mu
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File configs/config.lattepanda_mu:
https://review.coreboot.org/c/coreboot/+/83719/comment/51363ed0_91fa28dc?us… :
PS7, Line 3: CONFIG_FSP_FD_PATH="3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd"
this is the default from the Alderlake Kconfig, so this shouldn't be needed. i think the next two lines are also the defaults, but haven't checked in detail
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(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00
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vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00
Update generated FSP headers for ADL-N to MR5(5132_00)
Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7
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M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h
4 files changed, 2,648 insertions(+), 1,037 deletions(-)
Approvals:
Martin L Roth: Looks good to me, approved
build bot (Jenkins): Verified
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Change subject: b64_decode-test: Properly terminate strings before comparison
......................................................................
Patch Set 1: Code-Review+2
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Change subject: b64_decode-test: Properly terminate strings before comparison
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84088/comment/1e14e3f7_cd83d99a?us… :
PS1, Line 10: encoded
> No, quite the encoded or `.enc` in the code. In […]
Ah, I see what you mean. Thanks for clarifying.
I think the commit message is fine as is.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 50:
(10 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/70e33435_fa397870?us… :
PS38, Line 2:
> Added all mentioned, except "SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID"
> Moved this config to ACPI CL.
SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID should be selected as part of this CL.
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/bd5dbd70_d5b9312d?us… :
PS50, Line 21: FSP_UGOP_EARLY_SIGN_OF_LIFE
do you wish to select this now better add it when you have capable FSP to support uGOP?
https://review.coreboot.org/c/coreboot/+/83798/comment/93ca0af6_b0572eb8?us… :
PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18
I don't believe the ME spec is 18 for PTL. Please submit the common code changes for cse_spec.c at first place to reflect the correct ME version for PTL.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83798/comment/f0620a62_4d719059?us… :
PS50, Line 43: PTL_U_404_15W_CORE,
: PTL_H_484_25W_CORE,
: PTL_H_484_45W_CORE,
Why are you changing this macro? Without an explicit comment, it is difficult to follow what the magic numbers like `404` and `484` actually refer to.
https://review.coreboot.org/c/coreboot/+/83798/comment/7bfdc0b3_8195832e?us… :
PS50, Line 51: TDP_15W = 15
then you should have added other TDP macros as well ? as per my understanding we are actually starting with PTL-UH which is 25W.
https://review.coreboot.org/c/coreboot/+/83798/comment/4a718032_65a697ff?us… :
PS50, Line 60: PCI_DID_INTEL_PTL_U_ID_1
based on my understanding, we will also use `PCI_DID_INTEL_PTL_H_ID_1` for sometime (till next year) then in that case, we need to keep PCI_DID_INTEL_PTL_H_ID_1 and support configuration also enable (for 25W)
https://review.coreboot.org/c/coreboot/+/83798/comment/9349369e_61eb172f?us… :
PS50, Line 344: hybrid_storage_mode
this is not applicable since MTL. please check
https://review.coreboot.org/c/coreboot/+/83798/comment/b35852dd_4ef0943b?us… :
PS50, Line 363: dmi_pwr_optimize_disable
who is the consumer ? (I don't see anything during MTL). Also not sure if the DMI is still valid for PTL
File src/soc/intel/pantherlake/chip.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/b8d5ce1f_dc1a1e5c?us… :
PS50, Line 165: config
don;t we need the NULL check ?
File src/soc/intel/pantherlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/798aa821_2eec33bd?us… :
PS50, Line 165: conf
check for the NULL pointer
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