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Change subject: cpu/x86: Don't do partial linking
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/byra/var/kinox: Add/update VBT files
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
This CL breaks chromiumos as vbts are not installed the way this CL installed them, so the build breaks complaining that a vbt is already in the cbfs.
Setting copy-bot skip to allow coreboot downstreaming to continue.
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84088?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: b64_decode-test: Properly terminate strings before comparison
......................................................................
b64_decode-test: Properly terminate strings before comparison
Undefined behavior in unit-tests is no fun. assert_string_equal()
expects properly zero-terminated strings. None of the encoded test
strings contain a termination, hence add it manually.
Without this change, the test was often failing with a wrong error
message:
[==========] tests_lib_b64_decode-test(tests): Running 1 test(s).
[ RUN ] test_b64_decode
[ ERROR ] --- "AB" != "AB"
[ LINE ] --- tests/lib/b64_decode-test.c:38: error: Failure!
[ FAILED ] test_b64_decode
[==========] tests_lib_b64_decode-test(tests): 1 test(s) run.
Probably due to unprintable characters in the string. No idea why
my system is more susceptible to this issue.
Change-Id: Id1bd2c3ff06bc1d4e5aa21ddd0f1d5802540999d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84088
Reviewed-by: Jakub Czapiga <czapiga(a)google.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M tests/lib/b64_decode-test.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
Paul Menzel: Looks good to me, but someone else must approve
Matt DeVillier: Looks good to me, approved
Nicholas Sudsgaard: Looks good to me, approved
Jakub Czapiga: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/tests/lib/b64_decode-test.c b/tests/lib/b64_decode-test.c
index 189ce96..8560eb2 100644
--- a/tests/lib/b64_decode-test.c
+++ b/tests/lib/b64_decode-test.c
@@ -35,6 +35,9 @@
res = b64_decode((uint8_t *)messages[i].enc, strlen(messages[i].enc), decoded);
assert_int_equal(res, (strlen(messages[i].dec)));
+
+ decoded[res] = 0x00;
+
assert_string_equal((const char *)decoded, messages[i].dec);
free(decoded);
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Change subject: b64_decode-test: Properly terminate strings before comparison
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84088/comment/95070a57_1e642613?us… :
PS1, Line 12:
> Add test output failure before your change?
Done
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Hello Jakub Czapiga, Matt DeVillier, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84088?usp=email
to look at the new patch set (#2).
Change subject: b64_decode-test: Properly terminate strings before comparison
......................................................................
b64_decode-test: Properly terminate strings before comparison
Undefined behavior in unit-tests is no fun. assert_string_equal()
expects properly zero-terminated strings. None of the encoded test
strings contain a termination, hence add it manually.
Without this change, the test was often failing with a wrong error
message:
[==========] tests_lib_b64_decode-test(tests): Running 1 test(s).
[ RUN ] test_b64_decode
[ ERROR ] --- "AB" != "AB"
[ LINE ] --- tests/lib/b64_decode-test.c:38: error: Failure!
[ FAILED ] test_b64_decode
[==========] tests_lib_b64_decode-test(tests): 1 test(s) run.
Probably due to unprintable characters in the string. No idea why
my system is more susceptible to this issue.
Change-Id: Id1bd2c3ff06bc1d4e5aa21ddd0f1d5802540999d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M tests/lib/b64_decode-test.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/84088/2
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Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email )
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/400ce9c4_147eb679?us… :
PS14, Line 32: FSPM_MAX_NONTURBO_FREQ
> Last time I enquired PnP team they mentioned that P1 frequency and Boot frequency are different .
> I dont have expertise on this - I will find out and get back to you.
P1 = HFM and BootFrequency is meant to provide some guaranteed number
```
0: Maximum battery performance.
1: Maximum non-turbo performance. <--- this is ideally P1
2: Turbo performance <---- turbo hasn't been enabled so early.
```
You can take a look into FSP code, the code is self-explanatory IMO. BSP always boots in P1 freq if the equivalent soft-strap has been set in MFIT.
Ideally BootFrequency UPD is used to override the CPU flex Ratio apart of using yet another UPD CpuRatio. CPU flex ratio strap is always overridden using CpuRatio UPD where BootFrequency is just yet another option. Therefore, you are actually overriding the same CPU soft-strap.
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Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75286?usp=email )
Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS10:
Intel tried to remove support for FCM with Barlow Ridge, and then added it back for r1.1+. But it's basically unsupported and SCM should be used.
Duplicating all the SoC iTBT logic for SCM support doesn't seem great, but SoC code might have to be modified regardless of where dTBT is implemented.
File src/drivers/intel/dtbt/dtbt.c:
https://review.coreboot.org/c/coreboot/+/75286/comment/ca37c029_aaea9e6d?us… :
PS10, Line 15: #define PCIE2TBT_GO2SX 2
: #define PCIE2TBT_GO2SX_NO_WAKE 3
: #define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4
: #define PCIE2TBT_OS_UP 6
: #define PCIE2TBT_SET_SECURITY_LEVEL 8
: #define PCIE2TBT_GET_SECURITY_LEVEL 9
: #define PCIE2TBT_BOOT_ON 24
: #define PCIE2TBT_USB_ON 25
: #define PCIE2TBT_GET_ENUMERATION_METHOD 26
: #define PCIE2TBT_SET_ENUMERATION_METHOD 27
: #define PCIE2TBT_POWER_CYCLE 28
: #define PCIE2TBT_SX_START 29
: #define PCIE2TBT_ACL_BOOT 30
: #define PCIE2TBT_CONNECT_TOPOLOGY 31
> Barlow Ridge (TBT5) only supports the mailbox commands: […]
`Set_Class_Code` was removed in r1.1, and `MaxPayloadSize` was documented.
- 0x11: `MayPayloadSize`
- 0x24: `GO2SLEEP`
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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelley Chen, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brox/variants/brox/ramstage.c
4 files changed, 85 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/15
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