coreboot-gerrit August 2024

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[M] Change in coreboot[main]: mb/google/brox/jubilant: update overridetree for dptf settings
by Ren Kuo (Code Review) 27 Aug '24

27 Aug '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84100?usp=email ) Change subject: mb/google/brox/jubilant: update overridetree for dptf settings ...................................................................... mb/google/brox/jubilant: update overridetree for dptf settings Update dptf settings for EVT. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge Change-Id: I7f0656f9ce2b3b89ef908e152d346853634296e5 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 18 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84100/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 0613ff9..8665d28 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -45,75 +45,37 @@ register "options.tsr[1].desc" = ""Soc"" register "options.tsr[2].desc" = ""Charger"" - ## Active Policy - register "policies.active" = "{ - [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(95, 90), - TEMP_PCT(92, 80), - TEMP_PCT(89, 60), - TEMP_PCT(85, 40), - TEMP_PCT(80, 30), - } - }, - [1] = { - .target = DPTF_TEMP_SENSOR_0, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - }, - [2] = { - .target = DPTF_TEMP_SENSOR_1, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - } - }" - ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 18000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, - }, + .min_power = 15000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000, - } + .min_power = 41000, + .max_power = 41000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } }" ## Charger Performance Control (Control, mA) @@ -124,24 +86,6 @@ [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - device generic 0 alias dptf_policy on end end end # DTT -- To view, visit https://review.coreboot.org/c/coreboot/+/84100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f0656f9ce2b3b89ef908e152d346853634296e5 Gerrit-Change-Number: 84100 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 27 Aug '24

27 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#53). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,739 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 53 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 27 Aug '24

27 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 47: (1 comment) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83789/comment/a2d3792c_d8412292?us… : PS17, Line 263: Since Lunarlake, OS pinctrl no long provides SOC GPIO pincntrl info. : Rather, firmware is responsible for providing such info via APCI. : Firmware can provide entire PADs or excluding those non GPP_[group]_[number] : at the end of each community. > Our gpio pinctrl owner points me this link. https://intelpedia.intel.com/OTC_Intel_Linux_Wiki/KernelDev/Linux_Kernel_Kn… > > In the past, such as MTL, pinctrl module is kernel/drivers/pinctrl/intel/pinctrl-meteorlake.ko (ref: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/head…), which provides the Intel's SOC pad info. > In PTL, kernel/drivers/pinctrl/intel/pinctrl-intel-platform.ko is used ( ref: > https://github.com/torvalds/linux/blob/master/drivers/pinctrl/intel/pinctrl…), which gets the GPIO info via ACPI. There won't be pinctrl-pantherlake.ko. > > I will ask the owner for the discussion details in the community. these links are not accessible to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 47 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Aug 2024 07:39:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 52: (27 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/af284899_a6aa4479?us… : PS38, Line 2: > > Added all mentioned, except "SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID" […] Okay, added. https://review.coreboot.org/c/coreboot/+/83798/comment/4d1f28ac_48aeb548?us… : PS38, Line 190: # - 194 MiB Non-prefetchable memory : # - 448 MiB Prefetchable memory > you need to update the comments as well depending upon the hardcoded value Sure, have updated the comment as per below updated values. https://review.coreboot.org/c/coreboot/+/83798/comment/76816c24_bae9d5c2?us… : PS38, Line 198: config PCIEXP_HOTPLUG_MEM : hex : default 0x6000000 : : config PCIEXP_HOTPLUG_PREFETCH_MEM : hex : default 0x800000000 > please specify the source of this magic numbers Updated the values. There is no change from previous platform. File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83798/comment/1ed7f895_3ffb4d51?us… : PS50, Line 21: FSP_UGOP_EARLY_SIGN_OF_LIFE > do you wish to select this now better add it when you have capable FSP to support uGOP? Sure, marking it TODO in crosbug. https://review.coreboot.org/c/coreboot/+/83798/comment/1d7b309b_feac0127?us… : PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 > I don't believe the ME spec is 18 for PTL. Please submit the common code changes for cse_spec. […] Sure. File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/e057c565_6ce3ddaf?us… : PS50, Line 43: PTL_U_404_15W_CORE, : PTL_H_484_25W_CORE, : PTL_H_484_45W_CORE, > Why are you changing this macro? Without an explicit comment, it is difficult to follow what the mag […] Hi Subrata, 404 means =(4 P-cores +0 E-cores + 4 LP E-cores) & 484 mean =(4 P-cores +8 E-cores + 4 LP Ecores). Is it Ok to carry forwaed this naming? About keeping comment, i have add them. Please let me know if this works. https://review.coreboot.org/c/coreboot/+/83798/comment/93a5d48a_84270a8d?us… : PS50, Line 51: TDP_15W = 15 > then you should have added other TDP macros as well ? as per my understanding we are actually start […] Sure, i have added 25W for PTL-UH Sku. https://review.coreboot.org/c/coreboot/+/83798/comment/bfce8339_355d5c3c?us… : PS50, Line 60: PCI_DID_INTEL_PTL_U_ID_1 > based on my understanding, we will also use `PCI_DID_INTEL_PTL_H_ID_1` for sometime (till next year) […] Sure, added the corresponding PTL-H amd its support config. https://review.coreboot.org/c/coreboot/+/83798/comment/21167e8d_e6d72162?us… : PS50, Line 344: hybrid_storage_mode > this is not applicable since MTL. […] Removed, no UPD consumer in PTL. https://review.coreboot.org/c/coreboot/+/83798/comment/63cffe22_6936cad6?us… : PS50, Line 363: dmi_pwr_optimize_disable > who is the consumer ? (I don't see anything during MTL). […] Removed, no consumer in PTL as well. https://review.coreboot.org/c/coreboot/+/83798/comment/ede4b9a7_e6120228?us… : PS50, Line 408: }; > during MTL, we had one useful UPD `lower_basic_mem_test_size` which is now not listed under PTL chip […] lower_basic_mem_test_size is avaliable in PTL. Added to chip.h. As suggested, i have added the useful UPDs that existed into MTL. Will capture thise in to TODO crosbug for its updation. File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/35985f94_1ddb32b1?us… : PS50, Line 12: #include <intelblocks/gpio.h> > do we need this header ? Not required. Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/ac17c77c_6d5fc581?us… : PS50, Line 165: config > don;t we need the NULL check ? Added the NULL check. File src/soc/intel/pantherlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/83798/comment/c710c57f_ad0eb88a?us… : PS50, Line 10: > can you please add a power limit entry for 25W SoC? we will be using PTL-UH for sometime Sure, i have added all the power limit entries for all avaliable SKUs. https://review.coreboot.org/c/coreboot/+/83798/comment/8cb24823_509e59af?us… : PS50, Line 119: shared_sram > isn't this is still known as `pmc_shared_sram` ? Changed to pmc_shared_sram. File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/35307601_a1503a40?us… : PS50, Line 165: conf > check for the NULL pointer Sure, added. File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/641c5f0d_b46ff7ff?us… : PS50, Line 44: > use tab? Acknowledged File src/soc/intel/pantherlake/include/soc/crashlog.h: https://review.coreboot.org/c/coreboot/+/83798/comment/8d763305_e5faa20a?us… : PS50, Line 11: #define TEL_DVSEC_NEXT_CAP 0x2 > same No consumer. Removed. https://review.coreboot.org/c/coreboot/+/83798/comment/19e954b9_bfacd934?us… : PS50, Line 21: #define CRASHLOG_POINTER_SIZE_FIELD_OFFSET 0x04 > who is the consumer ? No consumer. Removed. File src/soc/intel/pantherlake/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/83798/comment/218193bf_d50af2f8?us… : PS50, Line 53: DSM_BASE_ADDR_REG > why we need this when we have below macro in common code systemagent.h […] Ack, changed to use BDSM. https://review.coreboot.org/c/coreboot/+/83798/comment/001e101c_64544c2f?us… : PS50, Line 54: DPR_REG > same true for […] Ack, Removed. File src/soc/intel/pantherlake/p2sb.c: https://review.coreboot.org/c/coreboot/+/83798/comment/1d693119_bfddc721?us… : PS50, Line 53: soc > as this is local SOC code, can you please check if you can rename `soc_p2sb_ops` to `pcd_p2sb_ops` ? Sure, updated to pcd_p2sb_ops File src/soc/intel/pantherlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/83798/comment/727e255f_0bc2d4f7?us… : PS50, Line 32: > same Acknowledged https://review.coreboot.org/c/coreboot/+/83798/comment/5aade248_417f70ea?us… : PS50, Line 64: > same Acknowledged https://review.coreboot.org/c/coreboot/+/83798/comment/378cca77_a040ef82?us… : PS50, Line 91: > avoid empty line Sure, removed. https://review.coreboot.org/c/coreboot/+/83798/comment/4d8cf747_47c4c143?us… : PS50, Line 249: return (uint16_t) ACPI_BASE_ADDRESS; > ``` […] Acknowledged File src/soc/intel/pantherlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/83798/comment/14cc3fd2_932a8e7f?us… : PS50, Line 103: DSM_BASE_ADDR_REG > `BDSM` is enough. Sure, updated to use BDSM from <intelblocks/systemagent.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 52 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 07:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#52). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,691 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/52 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 52 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: dsm:dsm test [not to merge]. To test
by Poornima Tom (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Poornima Tom. Hello Poornima Tom, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84096?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: dsm:dsm test [not to merge]. To test ...................................................................... dsm:dsm test [not to merge]. To test Change-Id: I979ddb5a9993a491ea48edaaf2a5ad2653430799 Signed-off-by: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84096/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I979ddb5a9993a491ea48edaaf2a5ad2653430799 Gerrit-Change-Number: 84096 Gerrit-PatchSet: 2 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Shuo Liu (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 15: (10 comments) File src/soc/intel/snowridge/Kconfig: https://review.coreboot.org/c/coreboot/+/83321/comment/3eb68f2c_d73a7a18?us… : PS15, Line 42: select FSP_T_XIP Should FSP_S_XIP be selected as well? https://review.coreboot.org/c/coreboot/+/83321/comment/37f641fe_d9ee440f?us… : PS15, Line 123: default 0x3ff00 if FSP_CAR Are FSP_CAR and !FSP_CAR both validated? https://review.coreboot.org/c/coreboot/+/83321/comment/a41daac6_ed51c2df?us… : PS15, Line 244: 0xfe00000. It will be used until coreboot resource allocation overwrite it 0xfe000000? File src/soc/intel/snowridge/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83321/comment/82ebec05_65ba309b?us… : PS15, Line 60: endif ## CONFIG_SOC_INTEL_FSP_SNOWRIDGE CONFIG_SOC_INTEL_SNOWRIDGE File src/soc/intel/snowridge/chip.h: https://review.coreboot.org/c/coreboot/+/83321/comment/06f3c18a_52a2d278?us… : PS15, Line 12: * additional root bus in stack 2 and 7 (UBox1). So what is for stack 2? File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/0caa4002_0b24f221?us… : PS15, Line 55: const BL_IIO_UDS *hob; Could you please follow C99 practice that declaring variable when using? https://review.coreboot.org/c/coreboot/+/83321/comment/3b0a1615_bf2cdb36?us… : PS15, Line 75: if (sr[i].Personality >= BL_TYPE_DISABLED) is there any reason not using !=? https://review.coreboot.org/c/coreboot/+/83321/comment/d07132e2_1fcdda2e?us… : PS15, Line 180: int i; for (int i = 0; ...) File src/soc/intel/snowridge/systemagent.c: https://review.coreboot.org/c/coreboot/+/83321/comment/3992c000_6f93598d?us… : PS15, Line 17: *size = CONFIG_ECAM_MMCONF_LENGTH; Shouldn't be probed by BAR access? https://review.coreboot.org/c/coreboot/+/83321/comment/a4616d7b_e875dace?us… : PS15, Line 33: { The resource_cnt is a bit confusing, is there cases where resource_cnt != 1? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 15 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Aug 2024 07:21:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/common/systemagent: Improve systemagent
by Shuo Liu (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Felix Held, Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Improve systemagent ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: Not sure if we need to split to multiple patches to be more clear, but the overall changes LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 13 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 27 Aug 2024 06:44:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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