coreboot-gerrit August 2024

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[S] Change in coreboot[main]: soc/amd/common/psp/psp_def: rework command buffer documentation
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84061?usp=email ) Change subject: soc/amd/common/psp/psp_def: rework command buffer documentation ...................................................................... soc/amd/common/psp/psp_def: rework command buffer documentation The existing comment on the mbox_default_buffer struct was outdated and didn't reflect the current state, so rework it to keep it a bit more generic and also add the document number for the newer generations of CPUs. To better document which commands use non-default buffers, add the names of the commands using the non-default buffers to those buffer struct definitions. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I510d953217240243392e8a415358524257bd28b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84061 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp_def.h 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index c2b2fca..03fd352 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -48,12 +48,11 @@ } __packed; /* - * command-specific buffer definitions: see NDA document #54267 - * The following commands need a buffer definition if they are to be used. - * All other commands will work with the default buffer. - * MBOX_BIOS_CMD_SMM_INFO MBOX_BIOS_CMD_PSP_QUERY - * MBOX_BIOS_CMD_SX_INFO MBOX_BIOS_CMD_S3_DATA_INFO - * MBOX_BIOS_CMD_RSM_INFO + * x86 to PSP mailbox commands that don't take any parameter or return any data, use the + * mbox_default_buffer, while x86 to PSP commands that either pass data to the PSP or get data + * returned from the PSP use command-specific buffer definitions. For details on the specific + * buffer definitions for the various commands, see NDA document #54267 for the generations + * before family 17h and NDA document #55758 for the generations from family 17h on. */ struct mbox_default_buffer { /* command-response buffer unused by command */ @@ -73,16 +72,19 @@ uint64_t psp_mbox_smm_flag_address; } __packed; +/* MBOX_BIOS_CMD_SMM_INFO */ struct mbox_cmd_smm_info_buffer { struct mbox_buffer_header header; struct smm_req_buffer req; } __packed __aligned(32); +/* MBOX_BIOS_CMD_SX_INFO */ struct mbox_cmd_sx_info_buffer { struct mbox_buffer_header header; u8 sleep_type; } __packed __aligned(32); +/* MBOX_BIOS_CMD_SET_SPL_FUSE */ struct mbox_cmd_late_spl_buffer { struct mbox_buffer_header header; uint32_t spl_value; @@ -99,6 +101,7 @@ DTPM_REQUEST_MAX, }; +/* MBOX_BIOS_CMD_I2C_TPM_ARBITRATION */ struct mbox_cmd_dtpm_config_buffer { struct mbox_buffer_header header; uint32_t request_type; -- To view, visit https://review.coreboot.org/c/coreboot/+/84061?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I510d953217240243392e8a415358524257bd28b1 Gerrit-Change-Number: 84061 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: payloads/Kconfig: Fix dependencies of PAYLOAD_FIT_SUPPORT
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84086?usp=email ) Change subject: payloads/Kconfig: Fix dependencies of PAYLOAD_FIT_SUPPORT ...................................................................... payloads/Kconfig: Fix dependencies of PAYLOAD_FIT_SUPPORT Move config PAYLOAD_FIT_SUPPORT out of the `if !PAYLOAD_NONE'. It's independent of the choice to add a payload right away. Change-Id: I4b9cd13bf017d4afc30d1599ecc2faaf87bf0213 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84086 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/Kconfig 1 file changed, 11 insertions(+), 11 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/Kconfig b/payloads/Kconfig index ec1d40c..4948624 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -103,17 +103,6 @@ bool default n -config PAYLOAD_FIT_SUPPORT - bool "FIT support" - default n - default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) - depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM - select FLATTENED_DEVICE_TREE - help - Select this option if your payload is of type FIT. - Enables FIT parser and devicetree patching. The FIT is non - self-extracting and needs to have a compatible compression format. - config COMPRESS_SECONDARY_PAYLOAD bool "Use LZMA compression for secondary payloads" default y @@ -191,4 +180,15 @@ endif # !PAYLOAD_NONE +config PAYLOAD_FIT_SUPPORT + bool "FIT support" + default n + default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM + select FLATTENED_DEVICE_TREE + help + Select this option if your payload is of type FIT. + Enables FIT parser and devicetree patching. The FIT is non + self-extracting and needs to have a compatible compression format. + endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/84086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b9cd13bf017d4afc30d1599ecc2faaf87bf0213 Gerrit-Change-Number: 84086 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 55: (1 comment) File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/08d711d6_c0e3ca21?us… : PS50, Line 143: disable_three_strike_error > please check if below limitation still exists for PTL ESx and QSx samples ? […] sure, will check it. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 55 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 11:17:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Felix Held, Martin L Roth, Nicholas Chin. KunYi Chen has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 9: (1 comment) File configs/config.lattepanda_mu: https://review.coreboot.org/c/coreboot/+/83719/comment/c9b0e7d9_5ee3ac00?us… : PS7, Line 3: CONFIG_FSP_FD_PATH="3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" > this is the default from the Alderlake Kconfig, so this shouldn't be needed. […] okay, you are right remove the three lines now -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 9 Gerrit-Owner: KunYi Chen Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 27 Aug 2024 11:16:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by KunYi Chen (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Martin L Roth, Nicholas Chin. Hello Felix Held, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83719?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... mb/lattepanda: Add support for LattePanda Mu Add initial support for the LattePanda Mu board, which features: Intel Alder Lake-N N100 processor 8GB LPDDR5 memory 64GB eMMC storage SO-DIMM 260-pin connector for function expansion This commit includes: Basic board configuration Memory initialization Essential I/O setup Testing with Lite carrier board Booting into default installed Windows: Passed USB 3.0/2.0: Working HDMI output: Working Realtek Ethernet: Working S3 sleep mode: Failed Power on after shutdown: Failed (requires power removal) Installing Ubuntu 22.04: Failed UART of SuperIO in OS: Missing Environment Controller: Not supported M.2/M Key: Not working (booting failed with SSD 512GB installed) Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen(a)gmail.com> --- A configs/config.lattepanda_mu A src/mainboard/lattepanda/Kconfig A src/mainboard/lattepanda/Kconfig.name A src/mainboard/lattepanda/mu/Kconfig A src/mainboard/lattepanda/mu/Kconfig.name A src/mainboard/lattepanda/mu/Makefile.mk A src/mainboard/lattepanda/mu/board_info.txt A src/mainboard/lattepanda/mu/bootblock.c A src/mainboard/lattepanda/mu/data.vbt A src/mainboard/lattepanda/mu/devicetree.cb A src/mainboard/lattepanda/mu/dsdt.asl A src/mainboard/lattepanda/mu/gpio.c A src/mainboard/lattepanda/mu/include/baseboard/gpio.h A src/mainboard/lattepanda/mu/include/baseboard/variants.h A src/mainboard/lattepanda/mu/mainboard.c A src/mainboard/lattepanda/mu/memory.c A src/mainboard/lattepanda/mu/ramstage.c A src/mainboard/lattepanda/mu/romstage_fsp_params.c A src/mainboard/lattepanda/mu/spd/Makefile.mk A src/mainboard/lattepanda/mu/spd/empty.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_16gb.spd.hex A src/mainboard/lattepanda/mu/spd/mu_lp5_8gb.spd.hex 22 files changed, 759 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83719/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 9 Gerrit-Owner: KunYi Chen Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: KunYi Chen Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread
by Arthur Heymans (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84042?usp=email ) Change subject: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84042/comment/b20c6ca0_c355ede0?us… : PS8, Line 354: if (array_size > 0) > Hmmm, actually, why not move the check inside `print_num_status_bits()`? Done differently. -- To view, visit https://review.coreboot.org/c/coreboot/+/84042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Gerrit-Change-Number: 84042 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 10:58:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#55). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 41 files changed, 3,739 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/55 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 55 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread
by Nico Huber (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84042?usp=email ) Change subject: soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overread ...................................................................... Patch Set 11: Code-Review+2 (1 comment) Patchset: PS11: Seems to happen only for x86_64. I've looked at the compiled code (with -Wno-error=stringop-overread) to be sure, looks good to me: ``` 0000000004000791 <print_num_status_bits>: 4000791: 85 f6 test %esi,%esi 4000793: 74 68 je 40007fd <print_num_status_bits+0x6c> 4000795: 41 55 push %r13 4000797: 41 54 push %r12 4000799: 55 push %rbp 400079a: 53 push %rbx 400079b: 51 push %rcx 400079c: 89 f5 mov %esi,%ebp 400079e: 49 89 d4 mov %rdx,%r12 40007a1: ff cf dec %edi 40007a3: 48 63 df movslq %edi,%rbx 40007a6: 49 bd ff 19 02 04 00 movabs $0x40219ff,%r13 40007ad: 00 00 00 40007a8: R_X86_64_64 printk 40007b0: 89 d8 mov %ebx,%eax 40007b2: 85 db test %ebx,%ebx 40007b4: 78 3f js 40007f5 <print_num_status_bits+0x64> ``` `num_bits` should be in `%edi`, it's decremented, then checked... -- To view, visit https://review.coreboot.org/c/coreboot/+/84042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Gerrit-Change-Number: 84042 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Aug 2024 10:38:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common/systemagent: Improve systemagent
by Arthur Heymans (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Felix Held, Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Arthur Heymans has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Improve systemagent ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/b62145f8_fe3246e0?us… : PS13, Line 9: System agent in Intel common block (1) assumes TOLUD and TOUUD : registers hold the max available address plus 1, but on some SoC like : Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD : and TSEG registers to 1 MiB default, but some SoC may have different : alignments. This patch add a new weak function : `soc_systemagent_fixup_address()` to improve it. Can you not capture the different semantics of the registers in Kconfig, have SOC select it and keep the common code? The weak callbacks make it less clear what is going on. -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 13 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 27 Aug 2024 10:23:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Derek Huang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Derek Huang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 16: (2 comments) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/82682/comment/79ac0ab6_27a40394?us… : PS15, Line 546: return config->vccin_aux_imon_iccmax \ > `Avoid unnecessary line continuations` Please fix. https://review.coreboot.org/c/coreboot/+/82682/comment/0c2235de_7934dac4?us… : PS15, Line 1020: s_cfg->VccInAuxImonIccImax = \ > `Avoid unnecessary line continuations` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 09:54:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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