coreboot-gerrit August 2024

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, Sumeet R Pawnikar. Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 16: (2 comments) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/82682/comment/bda7f91b_99a2f18d?us… : PS15, Line 546: return config->vccin_aux_imon_iccmax \ > > `Avoid unnecessary line continuations` […] Done https://review.coreboot.org/c/coreboot/+/82682/comment/34862246_038e1537?us… : PS15, Line 1020: s_cfg->VccInAuxImonIccImax = \ > > `Avoid unnecessary line continuations` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 11:47:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: force audio mute to avoid screen flick
by Simon Yang (Code Review) 27 Aug '24

27 Aug '24

Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/84098?usp=email ) Change subject: mb/google/nissa/var/anraggar: force audio mute to avoid screen flick ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Gerrit-Change-Number: 84098 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Aug 2024 11:41:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/smihandler: add PSP SMI handler
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84077?usp=email ) Change subject: soc/amd/stoneyridge/smihandler: add PSP SMI handler ...................................................................... soc/amd/stoneyridge/smihandler: add PSP SMI handler Now that the PSP SMI handler for flash access is also implemented for the PSP generation 1, the PSP SMI handler can be added to the Stoneyridge code too. The actual PSP SMI handler code will only be added to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't the default case, so this patch doesn't change the current behavior unless that option is also selected. This SMI handler mainly added for completeness since the PSP firmware blobs released for Stoneyridge are probably lacking the corresponding PSP-side code to send the PSP SMI to the host. At least if I remember correctly the PSP bootloader release for Stoneyridge has the ability to load the secure OS removed and since the secure OS is the runtime component, some part of that is probably what's sending those SMIs to the host. If there are some other PSP bootloader builds that support loading the secure OS, this patch might still be useful for those. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84077 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index f962fa0..826dc2a 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/psp.h> #include <amdblocks/smi.h> #include <amdblocks/smm.h> #include <arch/hlt.h> @@ -136,6 +137,7 @@ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = stoneyridge_fch_apmc_smi_handler }, { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, + { .type = SMITYPE_PSP, .handler = psp_smi_handler }, }; void *get_smi_source_handler(int source) -- To view, visit https://review.coreboot.org/c/coreboot/+/84077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1 Gerrit-Change-Number: 84077 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/common/psp: move PSP SMI SPI access function prototypes
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84068?usp=email ) Change subject: soc/amd/common/psp: move PSP SMI SPI access function prototypes ...................................................................... soc/amd/common/psp: move PSP SMI SPI access function prototypes Now that we have the local psp_smi_flash.h header, move the psp_smi_spi_* function prototypes there. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I12cbbabf6a960836fe0c5dc1424c08550cb66a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84068 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smi_flash.h 3 files changed, 6 insertions(+), 5 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index e723c84..d1f57ac 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -153,9 +153,4 @@ void enable_psp_smi(void); -enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer); -enum mbox_p2c_status psp_smi_spi_read(struct mbox_default_buffer *buffer); -enum mbox_p2c_status psp_smi_spi_write(struct mbox_default_buffer *buffer); -enum mbox_p2c_status psp_smi_spi_erase(struct mbox_default_buffer *buffer); - #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_smi.c b/src/soc/amd/common/block/psp/psp_smi.c index be7d4cb..ccd03793 100644 --- a/src/soc/amd/common/block/psp/psp_smi.c +++ b/src/soc/amd/common/block/psp/psp_smi.c @@ -7,6 +7,7 @@ #include <device/mmio.h> #include <types.h> #include "psp_def.h" +#include "psp_smi_flash.h" /* PSP to x86 commands */ #define MBOX_PSP_CMD_SPI_INFO 0x83 diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.h b/src/soc/amd/common/block/psp/psp_smi_flash.h index 6f3eb97..c9c6a1c 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.h +++ b/src/soc/amd/common/block/psp/psp_smi_flash.h @@ -61,3 +61,8 @@ uint64_t *num_bytes, uint8_t **data); void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, uint64_t *target_nv_id, uint64_t *lba, uint64_t *num_blocks); + +enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer); +enum mbox_p2c_status psp_smi_spi_read(struct mbox_default_buffer *buffer); +enum mbox_p2c_status psp_smi_spi_write(struct mbox_default_buffer *buffer); +enum mbox_p2c_status psp_smi_spi_erase(struct mbox_default_buffer *buffer); -- To view, visit https://review.coreboot.org/c/coreboot/+/84068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12cbbabf6a960836fe0c5dc1424c08550cb66a7a Gerrit-Change-Number: 84068 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/amd/common/psp: consistently use uint[8,16,32,64]_t data types
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84067?usp=email ) Change subject: soc/amd/common/psp: consistently use uint[8,16,32,64]_t data types ...................................................................... soc/amd/common/psp: consistently use uint[8,16,32,64]_t data types Use the uint[8,16,32,64]_t data types everywhere instead of a mixture of uint[8,16,32,64]_t and u[8,16,32,64] data types for consistency. Suggested-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I36151ecf94619afaf690dbb73834fcff3c51fdac Reviewed-on: https://review.coreboot.org/c/coreboot/+/84067 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smi.c M src/soc/amd/common/block/psp/psp_smi_flash.c M src/soc/amd/common/block/psp/psp_smi_flash.h M src/soc/amd/common/block/psp/psp_smi_flash_gen1.c M src/soc/amd/common/block/psp/psp_smi_flash_gen2.c M src/soc/amd/common/block/psp/psp_smm.c 12 files changed, 105 insertions(+), 102 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 061e79d..1ab3385 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -77,7 +77,7 @@ * Notify PSP that the system is entering a sleep state. sleep_state uses the * same definition as Pm1Cnt[SlpTyp], typically 0, 1, 3, 4, 5. */ -void psp_notify_sx_info(u8 sleep_type); +void psp_notify_sx_info(uint8_t sleep_type); int psp_load_named_blob(enum psp_blob_type type, const char *name); diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 4ac7aaf..d605473 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -34,7 +34,7 @@ #define FUSE_STATUS_FUSING_ERR 0x0a #define FUSE_STATUS_BOOT_DONE 0x0b -static const char *psb_test_status_to_string(u32 status) +static const char *psb_test_status_to_string(uint32_t status) { switch (status) { case PSB_TEST_STATUS_PASS: @@ -66,7 +66,7 @@ } } -static const char *fuse_status_to_string(u32 status) +static const char *fuse_status_to_string(uint32_t status) { switch (status) { case FUSE_STATUS_SUCCESS: @@ -101,7 +101,7 @@ */ static enum cb_err psb_enable(void) { - u32 status; + uint32_t status; struct mbox_default_buffer buffer = { .header = { .size = sizeof(buffer) @@ -127,7 +127,7 @@ printk(BIOS_INFO, "PSB: HSTI = %x\n", status); - const u32 psb_test_status = status & PSB_TEST_STATUS_MASK; + const uint32_t psb_test_status = status & PSB_TEST_STATUS_MASK; if (psb_test_status != PSB_TEST_STATUS_PASS) { printk(BIOS_ERR, "PSB: %s\n", psb_test_status_to_string(psb_test_status)); @@ -150,7 +150,7 @@ return CB_ERR; } - const u32 fuse_status = read32(&buffer.header.status); + const uint32_t fuse_status = read32(&buffer.header.status); if (fuse_status != FUSE_STATUS_SUCCESS) { printk(BIOS_ERR, "PSB: %s\n", fuse_status_to_string(fuse_status)); return CB_ERR; diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index a8bb205..008052b 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -35,7 +35,7 @@ } } -static u32 rd_resp_sts(struct mbox_buffer_header *header) +static uint32_t rd_resp_sts(struct mbox_buffer_header *header) { return read32(&header->status); } diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 3cf2fc9..e723c84 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -45,8 +45,8 @@ * AMD reference code aligns and pads all buffers to 32 bytes. */ struct mbox_buffer_header { - u32 size; /* total size of buffer */ - u32 status; /* command status, filled by PSP if applicable */ + uint32_t size; /* total size of buffer */ + uint32_t status; /* command status, filled by PSP if applicable */ } __packed; /* @@ -83,7 +83,7 @@ /* MBOX_BIOS_CMD_SX_INFO */ struct mbox_cmd_sx_info_buffer { struct mbox_buffer_header header; - u8 sleep_type; + uint8_t sleep_type; } __packed __aligned(32); /* MBOX_BIOS_CMD_PSP_FTPM_QUERY, MBOX_BIOS_CMD_PSP_CAPS_QUERY */ @@ -144,7 +144,7 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); /* This command needs to be implemented by the generation specific code. */ -int send_psp_command(u32 command, void *buffer); +int send_psp_command(uint32_t command, void *buffer); enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities); enum cb_err psp_get_psp_capabilities(uint32_t *capabilities); diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 1227c2a..b3815f9 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -32,9 +32,9 @@ * cmd_response: pointer to command/response buffer */ struct pspv1_mbox { - u32 mbox_command; - u32 mbox_status; - u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ + uint32_t mbox_command; + uint32_t mbox_status; + uint64_t cmd_response; /* definition conflicts w/BKDG but matches agesa */ } __packed; static void *soc_get_mbox_address(void) @@ -64,17 +64,17 @@ return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); } -static u32 rd_mbox_sts(struct pspv1_mbox *mbox) +static uint32_t rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); } -static void wr_mbox_cmd(struct pspv1_mbox *mbox, u32 cmd) +static void wr_mbox_cmd(struct pspv1_mbox *mbox, uint32_t cmd) { write32(&mbox->mbox_command, cmd); } -static u32 rd_mbox_cmd(struct pspv1_mbox *mbox) +static uint32_t rd_mbox_cmd(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_command); } @@ -112,7 +112,7 @@ return -PSPSTS_CMD_TIMEOUT; } -int send_psp_command(u32 command, void *buffer) +int send_psp_command(uint32_t command, void *buffer) { struct pspv1_mbox *mbox = soc_get_mbox_address(); if (!mbox) @@ -153,7 +153,7 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; - u32 command; + uint32_t command; void *blob; switch (type) { diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index a587cda..2113b57 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -82,17 +82,17 @@ } union pspv2_mbox_command { - u32 val; + uint32_t val; struct pspv2_mbox_cmd_fields { - u16 mbox_status; - u8 mbox_command; - u32 reserved:6; - u32 recovery:1; - u32 ready:1; + uint16_t mbox_status; + uint8_t mbox_command; + uint32_t reserved:6; + uint32_t recovery:1; + uint32_t ready:1; } __packed fields; }; -static u16 rd_mbox_sts(uintptr_t psp_mmio) +static uint16_t rd_mbox_sts(uintptr_t psp_mmio) { union pspv2_mbox_command tmp; @@ -100,7 +100,7 @@ return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, u8 cmd) +static void wr_mbox_cmd(uintptr_t psp_mmio, uint8_t cmd) { union pspv2_mbox_command tmp = { .val = 0 }; @@ -109,7 +109,7 @@ write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static u8 rd_mbox_recovery(uintptr_t psp_mmio) +static uint8_t rd_mbox_recovery(uintptr_t psp_mmio) { union pspv2_mbox_command tmp; @@ -127,7 +127,7 @@ union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; struct stopwatch sw; - u32 tmp; + uint32_t tmp; /* Zero fields from and_mask that should be kept */ and_mask.fields.mbox_command = 0; @@ -149,7 +149,7 @@ return -PSPSTS_CMD_TIMEOUT; } -int send_psp_command(u32 command, void *buffer) +int send_psp_command(uint32_t command, void *buffer) { const uintptr_t psp_mmio = get_psp_mmio_base(); if (!psp_mmio) diff --git a/src/soc/amd/common/block/psp/psp_smi.c b/src/soc/amd/common/block/psp/psp_smi.c index 66e84d1..be7d4cb 100644 --- a/src/soc/amd/common/block/psp/psp_smi.c +++ b/src/soc/amd/common/block/psp/psp_smi.c @@ -15,7 +15,7 @@ #define MBOX_PSP_CMD_SPI_ERASE 0x86 extern struct { - u8 buffer[P2C_BUFFER_MAXSIZE]; + uint8_t buffer[P2C_BUFFER_MAXSIZE]; } __aligned(32) p2c_buffer; static const uintptr_t p2c_mbox_base = (uintptr_t)&p2c_buffer.buffer; @@ -26,15 +26,15 @@ union p2c_mbox_status { struct { - u32 checksum : 8; /* [ 0.. 7] */ - u32 checksum_en : 1; /* [ 8.. 8] */ - u32 reserved : 22; /* [ 9..30] */ - u32 command_ready : 1; /* [31..31] */ + uint32_t checksum : 8; /* [ 0.. 7] */ + uint32_t checksum_en : 1; /* [ 8.. 8] */ + uint32_t reserved : 22; /* [ 9..30] */ + uint32_t command_ready : 1; /* [31..31] */ } __packed fields; - u32 raw; + uint32_t raw; }; -static u8 rd_bios_mbox_checksum(void) +static uint8_t rd_bios_mbox_checksum(void) { union p2c_mbox_status status; @@ -42,7 +42,7 @@ return status.fields.checksum; } -static void wr_bios_mbox_checksum(u8 checksum) +static void wr_bios_mbox_checksum(uint8_t checksum) { union p2c_mbox_status status; @@ -83,7 +83,7 @@ write32p(p2c_mbox_base + P2C_MBOX_COMMAND_OFFSET, 0); } -static u32 get_psp_command(void) +static uint32_t get_psp_command(void) { return read32p(p2c_mbox_base + P2C_MBOX_COMMAND_OFFSET); } @@ -98,11 +98,11 @@ return read32(&get_psp_command_buffer()->header.size); } -static u8 calc_psp_buffer_checksum8(void) +static uint8_t calc_psp_buffer_checksum8(void) { - const uint8_t *data = (const u8 *)get_psp_command_buffer(); + const uint8_t *data = (const uint8_t *)get_psp_command_buffer(); const size_t size = get_psp_cmd_buffer_length(); - u8 checksum = 0; + uint8_t checksum = 0; size_t i; for (i = 0; i < size; i++) @@ -131,7 +131,7 @@ static void handle_psp_command(void) { enum mbox_p2c_status status; - u32 cmd; + uint32_t cmd; struct mbox_default_buffer *const buffer = get_psp_command_buffer(); status = check_psp_command(); diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index e9b906b..ab9bc6c 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -12,16 +12,16 @@ #include "psp_smi_flash.h" static bool is_valid_rw_byte_count(struct mbox_psp_cmd_spi_read_write *cmd_buf, - u64 num_bytes) + uint64_t num_bytes) { - const u32 cmd_buf_size = read32(&cmd_buf->header.size); + const uint32_t cmd_buf_size = read32(&cmd_buf->header.size); const size_t payload_buffer_offset = offsetof(struct mbox_psp_cmd_spi_read_write, req) + offsetof(struct psp_spi_read_write_request, buffer); return num_bytes <= cmd_buf_size - payload_buffer_offset; } -static const char *id_to_region_name(u64 target_nv_id) +static const char *id_to_region_name(uint64_t target_nv_id) { switch (target_nv_id) { case SMI_TARGET_NVRAM: @@ -36,7 +36,7 @@ * Do not cache the location to cope with flash changing underneath (e.g. due * to an update) */ -static int lookup_store(u64 target_nv_id, struct region_device *rstore) +static int lookup_store(uint64_t target_nv_id, struct region_device *rstore) { /* read_rdev, write_rdev and store_irdev need to be static to not go out of scope when this function returns */ @@ -66,7 +66,7 @@ return rdev_chain(rstore, rdev, 0, region_device_sz(rdev)); } -static enum mbox_p2c_status find_psp_spi_flash_device_region(u64 target_nv_id, +static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_id, struct region_device *store, const struct spi_flash **flash) { @@ -95,9 +95,9 @@ (struct mbox_psp_cmd_spi_info *)buffer; const struct spi_flash *flash; struct region_device store; - u64 target_nv_id; - u64 block_size; - u64 num_blocks; + uint64_t target_nv_id; + uint64_t block_size; + uint64_t num_blocks; enum mbox_p2c_status ret; printk(BIOS_SPEW, "PSP: SPI info request\n"); @@ -134,11 +134,11 @@ struct mbox_psp_cmd_spi_read_write *const cmd_buf = (struct mbox_psp_cmd_spi_read_write *)buffer; enum mbox_p2c_status ret; - u64 target_nv_id; - u64 lba; - u64 offset; - u64 num_bytes; - u8 *data; + uint64_t target_nv_id; + uint64_t lba; + uint64_t offset; + uint64_t num_bytes; + uint8_t *data; size_t addr; const struct spi_flash *flash; struct region_device store; @@ -183,11 +183,11 @@ struct mbox_psp_cmd_spi_read_write *const cmd_buf = (struct mbox_psp_cmd_spi_read_write *)buffer; enum mbox_p2c_status ret; - u64 target_nv_id; - u64 lba; - u64 offset; - u64 num_bytes; - u8 *data; + uint64_t target_nv_id; + uint64_t lba; + uint64_t offset; + uint64_t num_bytes; + uint8_t *data; size_t addr; const struct spi_flash *flash; struct region_device store; @@ -232,9 +232,9 @@ struct mbox_psp_cmd_spi_erase *const cmd_buf = (struct mbox_psp_cmd_spi_erase *)buffer; enum mbox_p2c_status ret; - u64 target_nv_id; - u64 lba; - u64 num_blocks; + uint64_t target_nv_id; + uint64_t lba; + uint64_t num_blocks; size_t addr; size_t num_bytes; const struct spi_flash *flash; diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.h b/src/soc/amd/common/block/psp/psp_smi_flash.h index 52144f8..6f3eb97 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.h +++ b/src/soc/amd/common/block/psp/psp_smi_flash.h @@ -10,11 +10,11 @@ struct psp_spi_info_request { #if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) - u64 target_nv_id; + uint64_t target_nv_id; #endif - u64 lba; - u64 block_size; - u64 num_blocks; + uint64_t lba; + uint64_t block_size; + uint64_t num_blocks; } __packed; struct mbox_psp_cmd_spi_info { @@ -24,12 +24,12 @@ struct psp_spi_read_write_request { #if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) - u64 target_nv_id; + uint64_t target_nv_id; #endif - u64 lba; - u64 offset; - u64 num_bytes; - u8 buffer[]; + uint64_t lba; + uint64_t offset; + uint64_t num_bytes; + uint8_t buffer[]; } __packed; struct mbox_psp_cmd_spi_read_write { @@ -39,10 +39,10 @@ struct psp_spi_erase_request { #if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) - u64 target_nv_id; + uint64_t target_nv_id; #endif - u64 lba; - u64 num_blocks; + uint64_t lba; + uint64_t num_blocks; } __packed; struct mbox_psp_cmd_spi_erase { @@ -53,10 +53,11 @@ bool is_valid_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf); bool is_valid_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf); bool is_valid_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf); -u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf); -void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, - u64 num_blocks); -void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, - u64 *lba, u64 *offset, u64 *num_bytes, u8 **data); -void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, - u64 *num_blocks); +uint64_t get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf); +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, uint64_t lba, uint64_t block_size, + uint64_t num_blocks); +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, + uint64_t *target_nv_id, uint64_t *lba, uint64_t *offset, + uint64_t *num_bytes, uint8_t **data); +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, uint64_t *target_nv_id, + uint64_t *lba, uint64_t *num_blocks); diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c index c9beddb..5c087ec 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c @@ -20,21 +20,22 @@ return true; } -u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) +uint64_t get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) { return SMI_TARGET_NVRAM; } -void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, - u64 num_blocks) +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, uint64_t lba, uint64_t block_size, + uint64_t num_blocks) { write64(&cmd_buf->req.lba, lba); write64(&cmd_buf->req.block_size, block_size); write64(&cmd_buf->req.num_blocks, num_blocks); } -void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, - u64 *lba, u64 *offset, u64 *num_bytes, u8 **data) +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, + uint64_t *target_nv_id, uint64_t *lba, uint64_t *offset, + uint64_t *num_bytes, uint8_t **data) { *target_nv_id = SMI_TARGET_NVRAM; *lba = read64(&cmd_buf->req.lba); @@ -43,8 +44,8 @@ *data = cmd_buf->req.buffer; } -void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, - u64 *num_blocks) +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, uint64_t *target_nv_id, + uint64_t *lba, uint64_t *num_blocks) { *target_nv_id = SMI_TARGET_NVRAM; *lba = read64(&cmd_buf->req.lba); diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c index f62cdd2..70e4bc4 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c @@ -5,7 +5,7 @@ #include "psp_def.h" #include "psp_smi_flash.h" -static bool is_valid_psp_spi_id(u64 target_nv_id) +static bool is_valid_psp_spi_id(uint64_t target_nv_id) { return target_nv_id == SMI_TARGET_NVRAM || target_nv_id == SMI_TARGET_RPMC_NVRAM; @@ -26,21 +26,22 @@ return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); } -u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) +uint64_t get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) { return read64(&cmd_buf->req.target_nv_id); } -void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, - u64 num_blocks) +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, uint64_t lba, uint64_t block_size, + uint64_t num_blocks) { write64(&cmd_buf->req.lba, lba); write64(&cmd_buf->req.block_size, block_size); write64(&cmd_buf->req.num_blocks, num_blocks); } -void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, - u64 *lba, u64 *offset, u64 *num_bytes, u8 **data) +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, + uint64_t *target_nv_id, uint64_t *lba, uint64_t *offset, + uint64_t *num_bytes, uint8_t **data) { *target_nv_id = read64(&cmd_buf->req.target_nv_id); *lba = read64(&cmd_buf->req.lba); @@ -49,8 +50,8 @@ *data = cmd_buf->req.buffer; } -void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, - u64 *num_blocks) +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, uint64_t *target_nv_id, + uint64_t *lba, uint64_t *num_blocks) { *target_nv_id = read64(&cmd_buf->req.target_nv_id); *lba = read64(&cmd_buf->req.lba); diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 00e00dd..671942b 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -18,7 +18,7 @@ * buffer. */ struct { - u8 buffer[C2P_BUFFER_MAXSIZE]; + uint8_t buffer[C2P_BUFFER_MAXSIZE]; } __aligned(32) c2p_buffer; /* @@ -26,7 +26,7 @@ * and then send an SMI to the host to process the request. */ struct { - u8 buffer[P2C_BUFFER_MAXSIZE]; + uint8_t buffer[P2C_BUFFER_MAXSIZE]; } __aligned(32) p2c_buffer; /* @@ -45,7 +45,7 @@ smm_flag = 0; } -static int send_psp_command_smm(u32 command, void *buffer) +static int send_psp_command_smm(uint32_t command, void *buffer) { int cmd_status; @@ -106,7 +106,7 @@ } /* Notify PSP the system is going to a sleep state. */ -void psp_notify_sx_info(u8 sleep_type) +void psp_notify_sx_info(uint8_t sleep_type) { int cmd_status; struct mbox_cmd_sx_info_buffer *buffer; -- To view, visit https://review.coreboot.org/c/coreboot/+/84067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36151ecf94619afaf690dbb73834fcff3c51fdac Gerrit-Change-Number: 84067 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: soc/amd/common/psp: add helper functions to retrieve capability bits
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84066?usp=email ) Change subject: soc/amd/common/psp: add helper functions to retrieve capability bits ...................................................................... soc/amd/common/psp: add helper functions to retrieve capability bits Add helper functions to send the PSP commands to query the fTPM and PSP capability bits as well as the HSTI state. All SoCs using any PSP generation support the MBOX_BIOS_CMD_PSP_FTPM_QUERY command and some generation 1 and all generation 2 PSP SoCs support the MBOX_BIOS_CMD_HSTI_QUERY command, so implement those two in the common psp.c. Only PSP generation 2 supports the MBOX_BIOS_CMD_PSP_CAPS_QUERY command, so implement that one in psp_gen2.c. This code is ported and modified from github.com/teslamotors/coreboot/tree/tesla-4.12-amd Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e17f994fb332690828c55742262da793e297d99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84066 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 3 files changed, 86 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index f989a3b..a8bb205 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -55,6 +55,52 @@ printk(BIOS_DEBUG, "OK\n"); } +enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities) +{ + int cmd_status; + struct mbox_cmd_capability_query_buffer buffer = { + .header = { + .size = sizeof(buffer) + }, + }; + + printk(BIOS_DEBUG, "PSP: Querying fTPM capabilities..."); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_PSP_FTPM_QUERY, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + if (!cmd_status) + return CB_ERR; + + *capabilities = read32(&buffer.capabilities); + return CB_SUCCESS; +} + +enum cb_err psp_get_hsti_state(uint32_t *state) +{ + int cmd_status; + struct mbox_cmd_hsti_query_buffer buffer = { + .header = { + .size = sizeof(buffer) + }, + }; + + printk(BIOS_DEBUG, "PSP: Querying HSTI state..."); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_HSTI_QUERY, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + if (!cmd_status) + return CB_ERR; + + *state = read32(&buffer.state); + return CB_SUCCESS; +} + /* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index fa3ce36..3cf2fc9 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -23,7 +23,9 @@ #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_HSTI_QUERY 0x14 #define MBOX_BIOS_CMD_PSB_AUTO_FUSING 0x21 +#define MBOX_BIOS_CMD_PSP_CAPS_QUERY 0x27 #define MBOX_BIOS_CMD_SET_SPL_FUSE 0x2d #define MBOX_BIOS_CMD_QUERY_SPL_FUSE 0x47 #define MBOX_BIOS_CMD_I2C_TPM_ARBITRATION 0x64 @@ -84,6 +86,18 @@ u8 sleep_type; } __packed __aligned(32); +/* MBOX_BIOS_CMD_PSP_FTPM_QUERY, MBOX_BIOS_CMD_PSP_CAPS_QUERY */ +struct mbox_cmd_capability_query_buffer { + struct mbox_buffer_header header; + uint32_t capabilities; +} __packed __aligned(32); + +/* MBOX_BIOS_CMD_HSTI_QUERY */ +struct mbox_cmd_hsti_query_buffer { + struct mbox_buffer_header header; + uint32_t state; +} __packed __aligned(32); + /* MBOX_BIOS_CMD_SET_SPL_FUSE */ struct mbox_cmd_late_spl_buffer { struct mbox_buffer_header header; @@ -132,6 +146,9 @@ /* This command needs to be implemented by the generation specific code. */ int send_psp_command(u32 command, void *buffer); +enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities); +enum cb_err psp_get_psp_capabilities(uint32_t *capabilities); +enum cb_err psp_get_hsti_state(uint32_t *state); enum cb_err soc_read_c2p38(uint32_t *msg_38_value); void enable_psp_smi(void); diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index bed31c1..a587cda 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -177,6 +177,29 @@ return 0; } +enum cb_err psp_get_psp_capabilities(uint32_t *capabilities) +{ + int cmd_status; + struct mbox_cmd_capability_query_buffer buffer = { + .header = { + .size = sizeof(buffer) + }, + }; + + printk(BIOS_DEBUG, "PSP: Querying PSP capabilities..."); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_PSP_CAPS_QUERY, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + if (!cmd_status) + return CB_ERR; + + *capabilities = read32(&buffer.capabilities); + return CB_SUCCESS; +} + enum cb_err soc_read_c2p38(uint32_t *msg_38_value) { const uintptr_t psp_mmio = get_psp_mmio_base(); -- To view, visit https://review.coreboot.org/c/coreboot/+/84066?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e17f994fb332690828c55742262da793e297d99 Gerrit-Change-Number: 84066 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/amd/common/psp/psp_def: rename MBOX_BIOS_CMD_PSP_QUERY
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84065?usp=email ) Change subject: soc/amd/common/psp/psp_def: rename MBOX_BIOS_CMD_PSP_QUERY ...................................................................... soc/amd/common/psp/psp_def: rename MBOX_BIOS_CMD_PSP_QUERY Rename MBOX_BIOS_CMD_PSP_QUERY to MBOX_BIOS_CMD_PSP_FTPM_QUERY to bring it a bit more in line with document #55758 revision 2.04 and to avoid confusion when another command is added in a follow-up patch. In document #54267 revision 1.06 this command is called MBOX_BIOS_CMD_PSP_QUERY and in document #55758 revision 2.04 it's called MBOX_BIOS_CMD_FTPM_QUERY, so just name it MBOX_BIOS_CMD_PSP_FTPM_QUERY in coreboot which should be the least confusing name for it that still somewhat aligns with the documentation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id085b34363d39528bd125dfb77596d3ed13b6fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84065 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp_def.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 03fd352..fa3ce36 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -18,7 +18,7 @@ #define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 #define MBOX_BIOS_CMD_RSM_INFO 0x04 -#define MBOX_BIOS_CMD_PSP_QUERY 0x05 +#define MBOX_BIOS_CMD_PSP_FTPM_QUERY 0x05 #define MBOX_BIOS_CMD_BOOT_DONE 0x06 #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 -- To view, visit https://review.coreboot.org/c/coreboot/+/84065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id085b34363d39528bd125dfb77596d3ed13b6fa9 Gerrit-Change-Number: 84065 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: soc/amd/common/psp/psp_smi_flash: implement generation 1 support
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84064?usp=email ) Change subject: soc/amd/common/psp/psp_smi_flash: implement generation 1 support ...................................................................... soc/amd/common/psp/psp_smi_flash: implement generation 1 support Implement the request buffer access functions for the PSP generation 1 case. In this case, only the SMI_TARGET_NVRAM is supported, so always return this target NV ID and always return true in the validity checks which in the PSP generation 2 case check if the target NV ID is valid. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e141f846e930bab6972a281745c0180ac52c291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84064 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/psp/Makefile.mk A src/soc/amd/common/block/psp/psp_smi_flash_gen1.c 2 files changed, 54 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index 20e55e8..937cb8e 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -17,7 +17,9 @@ romstage-y += psp_gen1.c ramstage-y += psp_gen1.c + smm-y += psp_gen1.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen1.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c new file mode 100644 index 0000000..c9beddb --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <types.h> +#include "psp_def.h" +#include "psp_smi_flash.h" + +bool is_valid_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf) +{ + return true; +} + +bool is_valid_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf) +{ + return true; +} + +bool is_valid_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf) +{ + return true; +} + +u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) +{ + return SMI_TARGET_NVRAM; +} + +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, + u64 num_blocks) +{ + write64(&cmd_buf->req.lba, lba); + write64(&cmd_buf->req.block_size, block_size); + write64(&cmd_buf->req.num_blocks, num_blocks); +} + +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, + u64 *lba, u64 *offset, u64 *num_bytes, u8 **data) +{ + *target_nv_id = SMI_TARGET_NVRAM; + *lba = read64(&cmd_buf->req.lba); + *offset = read64(&cmd_buf->req.offset); + *num_bytes = read64(&cmd_buf->req.num_bytes); + *data = cmd_buf->req.buffer; +} + +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, + u64 *num_blocks) +{ + *target_nv_id = SMI_TARGET_NVRAM; + *lba = read64(&cmd_buf->req.lba); + *num_blocks = read64(&cmd_buf->req.num_blocks); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e141f846e930bab6972a281745c0180ac52c291 Gerrit-Change-Number: 84064 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: soc/amd/common/psp/psp_smi_flash: introduce common data structures
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84063?usp=email ) Change subject: soc/amd/common/psp/psp_smi_flash: introduce common data structures ...................................................................... soc/amd/common/psp/psp_smi_flash: introduce common data structures The request buffer data structures differ between the PSP generation 1 and 2 in the way that the generation 2 added the 64 bit target NV ID field right at the beginning of the request buffer data structures. In order to make the data structure definitions common, remove the target_nv_id struct element via the preprocessor in case the SOC_AMD_COMMON_BLOCK_PSP_GEN2 option isn't selected. Since the request buffer data structures are now common for both generations, also remove the 'v2' from the struct names. Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84063 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp_smi_flash.c M src/soc/amd/common/block/psp/psp_smi_flash.h M src/soc/amd/common/block/psp/psp_smi_flash_gen2.c 3 files changed, 40 insertions(+), 34 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index 8a62296..e9b906b 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -11,13 +11,13 @@ #include "psp_def.h" #include "psp_smi_flash.h" -static bool is_valid_rw_byte_count(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, +static bool is_valid_rw_byte_count(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 num_bytes) { const u32 cmd_buf_size = read32(&cmd_buf->header.size); const size_t payload_buffer_offset = - offsetof(struct mbox_pspv2_cmd_spi_read_write, req) + - offsetof(struct pspv2_spi_read_write_request, buffer); + offsetof(struct mbox_psp_cmd_spi_read_write, req) + + offsetof(struct psp_spi_read_write_request, buffer); return num_bytes <= cmd_buf_size - payload_buffer_offset; } @@ -91,8 +91,8 @@ enum mbox_p2c_status psp_smi_spi_get_info(struct mbox_default_buffer *buffer) { - struct mbox_pspv2_cmd_spi_info *const cmd_buf = - (struct mbox_pspv2_cmd_spi_info *)buffer; + struct mbox_psp_cmd_spi_info *const cmd_buf = + (struct mbox_psp_cmd_spi_info *)buffer; const struct spi_flash *flash; struct region_device store; u64 target_nv_id; @@ -131,8 +131,8 @@ enum mbox_p2c_status psp_smi_spi_read(struct mbox_default_buffer *buffer) { - struct mbox_pspv2_cmd_spi_read_write *const cmd_buf = - (struct mbox_pspv2_cmd_spi_read_write *)buffer; + struct mbox_psp_cmd_spi_read_write *const cmd_buf = + (struct mbox_psp_cmd_spi_read_write *)buffer; enum mbox_p2c_status ret; u64 target_nv_id; u64 lba; @@ -180,8 +180,8 @@ enum mbox_p2c_status psp_smi_spi_write(struct mbox_default_buffer *buffer) { - struct mbox_pspv2_cmd_spi_read_write *const cmd_buf = - (struct mbox_pspv2_cmd_spi_read_write *)buffer; + struct mbox_psp_cmd_spi_read_write *const cmd_buf = + (struct mbox_psp_cmd_spi_read_write *)buffer; enum mbox_p2c_status ret; u64 target_nv_id; u64 lba; @@ -229,8 +229,8 @@ enum mbox_p2c_status psp_smi_spi_erase(struct mbox_default_buffer *buffer) { - struct mbox_pspv2_cmd_spi_erase *const cmd_buf = - (struct mbox_pspv2_cmd_spi_erase *)buffer; + struct mbox_psp_cmd_spi_erase *const cmd_buf = + (struct mbox_psp_cmd_spi_erase *)buffer; enum mbox_p2c_status ret; u64 target_nv_id; u64 lba; diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.h b/src/soc/amd/common/block/psp/psp_smi_flash.h index 077cc3b..52144f8 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.h +++ b/src/soc/amd/common/block/psp/psp_smi_flash.h @@ -8,49 +8,55 @@ SMI_TARGET_RPMC_NVRAM = 5, }; -struct pspv2_spi_info_request { +struct psp_spi_info_request { +#if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) u64 target_nv_id; +#endif u64 lba; u64 block_size; u64 num_blocks; } __packed; -struct mbox_pspv2_cmd_spi_info { +struct mbox_psp_cmd_spi_info { struct mbox_buffer_header header; - struct pspv2_spi_info_request req; + struct psp_spi_info_request req; } __packed; -struct pspv2_spi_read_write_request { +struct psp_spi_read_write_request { +#if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) u64 target_nv_id; +#endif u64 lba; u64 offset; u64 num_bytes; u8 buffer[]; } __packed; -struct mbox_pspv2_cmd_spi_read_write { +struct mbox_psp_cmd_spi_read_write { struct mbox_buffer_header header; - struct pspv2_spi_read_write_request req; + struct psp_spi_read_write_request req; } __packed; -struct pspv2_spi_erase_request { +struct psp_spi_erase_request { +#if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2) u64 target_nv_id; +#endif u64 lba; u64 num_blocks; } __packed; -struct mbox_pspv2_cmd_spi_erase { +struct mbox_psp_cmd_spi_erase { struct mbox_buffer_header header; - struct pspv2_spi_erase_request req; + struct psp_spi_erase_request req; } __packed; -bool is_valid_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf); -bool is_valid_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf); -bool is_valid_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf); -u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf); -void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, +bool is_valid_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf); +bool is_valid_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf); +bool is_valid_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf); +u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf); +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, u64 num_blocks); -void get_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, u64 *lba, u64 *offset, u64 *num_bytes, u8 **data); -void get_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, u64 *num_blocks); diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c index 99ea030..f62cdd2 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c @@ -11,27 +11,27 @@ target_nv_id == SMI_TARGET_RPMC_NVRAM; } -bool is_valid_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf) +bool is_valid_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf) { return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); } -bool is_valid_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf) +bool is_valid_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf) { return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); } -bool is_valid_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf) +bool is_valid_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf) { return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); } -u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf) +u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf) { return read64(&cmd_buf->req.target_nv_id); } -void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, +void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, u64 num_blocks) { write64(&cmd_buf->req.lba, lba); @@ -39,7 +39,7 @@ write64(&cmd_buf->req.num_blocks, num_blocks); } -void get_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, +void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, u64 *lba, u64 *offset, u64 *num_bytes, u8 **data) { *target_nv_id = read64(&cmd_buf->req.target_nv_id); @@ -49,7 +49,7 @@ *data = cmd_buf->req.buffer; } -void get_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, +void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, u64 *num_blocks) { *target_nv_id = read64(&cmd_buf->req.target_nv_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/84063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a Gerrit-Change-Number: 84063 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: soc/amd/common/psp/psp_smi_flash: factor out generation-specific code
by Felix Held (Code Review) 27 Aug '24

27 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84062?usp=email ) Change subject: soc/amd/common/psp/psp_smi_flash: factor out generation-specific code ...................................................................... soc/amd/common/psp/psp_smi_flash: factor out generation-specific code Factor out the code to access the request buffer into PSP generation specific file. This is a preparation for adding PSP SMI flash access support for the PSP generation 1 which has a slightly different request buffer layout. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8e18f7ea53592d9fd413ad56e8d137cfc13ad5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/Makefile.mk M src/soc/amd/common/block/psp/psp_smi_flash.c A src/soc/amd/common/block/psp/psp_smi_flash.h A src/soc/amd/common/block/psp/psp_smi_flash_gen2.c 4 files changed, 116 insertions(+), 94 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index b72343c..20e55e8 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -29,6 +29,7 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c smm-y += psp_gen2.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen2.c smm-y += psp_smm_gen2.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index 405fc29..8a62296 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -9,100 +9,7 @@ #include <spi_flash.h> #include <types.h> #include "psp_def.h" - -enum psp_spi_id_type { - SMI_TARGET_NVRAM = 0, - SMI_TARGET_RPMC_NVRAM = 5, -}; - -struct pspv2_spi_info_request { - u64 target_nv_id; - u64 lba; - u64 block_size; - u64 num_blocks; -} __packed; - -struct mbox_pspv2_cmd_spi_info { - struct mbox_buffer_header header; - struct pspv2_spi_info_request req; -} __packed; - -struct pspv2_spi_read_write_request { - u64 target_nv_id; - u64 lba; - u64 offset; - u64 num_bytes; - u8 buffer[]; -} __packed; - -struct mbox_pspv2_cmd_spi_read_write { - struct mbox_buffer_header header; - struct pspv2_spi_read_write_request req; -} __packed; - -struct pspv2_spi_erase_request { - u64 target_nv_id; - u64 lba; - u64 num_blocks; -} __packed; - -struct mbox_pspv2_cmd_spi_erase { - struct mbox_buffer_header header; - struct pspv2_spi_erase_request req; -} __packed; - -static bool is_valid_psp_spi_id(u64 target_nv_id) -{ - return target_nv_id == SMI_TARGET_NVRAM || - target_nv_id == SMI_TARGET_RPMC_NVRAM; -} - -static bool is_valid_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf) -{ - return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); -} - -static bool is_valid_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf) -{ - return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); -} - -static bool is_valid_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf) -{ - return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); -} - -static u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf) -{ - return read64(&cmd_buf->req.target_nv_id); -} - -static void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf, - u64 lba, u64 block_size, u64 num_blocks) -{ - write64(&cmd_buf->req.lba, lba); - write64(&cmd_buf->req.block_size, block_size); - write64(&cmd_buf->req.num_blocks, num_blocks); -} - -static void get_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, - u64 *target_nv_id, u64 *lba, u64 *offset, - u64 *num_bytes, u8 **data) -{ - *target_nv_id = read64(&cmd_buf->req.target_nv_id); - *lba = read64(&cmd_buf->req.lba); - *offset = read64(&cmd_buf->req.offset); - *num_bytes = read64(&cmd_buf->req.num_bytes); - *data = cmd_buf->req.buffer; -} - -static void get_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf, - u64 *target_nv_id, u64 *lba, u64 *num_blocks) -{ - *target_nv_id = read64(&cmd_buf->req.target_nv_id); - *lba = read64(&cmd_buf->req.lba); - *num_blocks = read64(&cmd_buf->req.num_blocks); -} +#include "psp_smi_flash.h" static bool is_valid_rw_byte_count(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, u64 num_bytes) diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.h b/src/soc/amd/common/block/psp/psp_smi_flash.h new file mode 100644 index 0000000..077cc3b --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smi_flash.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include "psp_def.h" + +enum psp_spi_id_type { + SMI_TARGET_NVRAM = 0, + SMI_TARGET_RPMC_NVRAM = 5, +}; + +struct pspv2_spi_info_request { + u64 target_nv_id; + u64 lba; + u64 block_size; + u64 num_blocks; +} __packed; + +struct mbox_pspv2_cmd_spi_info { + struct mbox_buffer_header header; + struct pspv2_spi_info_request req; +} __packed; + +struct pspv2_spi_read_write_request { + u64 target_nv_id; + u64 lba; + u64 offset; + u64 num_bytes; + u8 buffer[]; +} __packed; + +struct mbox_pspv2_cmd_spi_read_write { + struct mbox_buffer_header header; + struct pspv2_spi_read_write_request req; +} __packed; + +struct pspv2_spi_erase_request { + u64 target_nv_id; + u64 lba; + u64 num_blocks; +} __packed; + +struct mbox_pspv2_cmd_spi_erase { + struct mbox_buffer_header header; + struct pspv2_spi_erase_request req; +} __packed; + +bool is_valid_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf); +bool is_valid_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf); +bool is_valid_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf); +u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf); +void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, + u64 num_blocks); +void get_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, + u64 *lba, u64 *offset, u64 *num_bytes, u8 **data); +void get_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, + u64 *num_blocks); diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c new file mode 100644 index 0000000..99ea030 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen2.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <types.h> +#include "psp_def.h" +#include "psp_smi_flash.h" + +static bool is_valid_psp_spi_id(u64 target_nv_id) +{ + return target_nv_id == SMI_TARGET_NVRAM || + target_nv_id == SMI_TARGET_RPMC_NVRAM; +} + +bool is_valid_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf) +{ + return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); +} + +bool is_valid_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf) +{ + return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); +} + +bool is_valid_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf) +{ + return is_valid_psp_spi_id(read64(&cmd_buf->req.target_nv_id)); +} + +u64 get_psp_spi_info_id(struct mbox_pspv2_cmd_spi_info *cmd_buf) +{ + return read64(&cmd_buf->req.target_nv_id); +} + +void set_psp_spi_info(struct mbox_pspv2_cmd_spi_info *cmd_buf, u64 lba, u64 block_size, + u64 num_blocks) +{ + write64(&cmd_buf->req.lba, lba); + write64(&cmd_buf->req.block_size, block_size); + write64(&cmd_buf->req.num_blocks, num_blocks); +} + +void get_psp_spi_read_write(struct mbox_pspv2_cmd_spi_read_write *cmd_buf, u64 *target_nv_id, + u64 *lba, u64 *offset, u64 *num_bytes, u8 **data) +{ + *target_nv_id = read64(&cmd_buf->req.target_nv_id); + *lba = read64(&cmd_buf->req.lba); + *offset = read64(&cmd_buf->req.offset); + *num_bytes = read64(&cmd_buf->req.num_bytes); + *data = cmd_buf->req.buffer; +} + +void get_psp_spi_erase(struct mbox_pspv2_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba, + u64 *num_blocks) +{ + *target_nv_id = read64(&cmd_buf->req.target_nv_id); + *lba = read64(&cmd_buf->req.lba); + *num_blocks = read64(&cmd_buf->req.num_blocks); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84062?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e18f7ea53592d9fd413ad56e8d137cfc13ad5d4 Gerrit-Change-Number: 84062 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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