coreboot-gerrit August 2024

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Felix Singer (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Arthur Heymans, Martin L Roth. Felix Singer has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84032?usp=email ) Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... Patch Set 8: (1 comment) File util/crossgcc/patches/clang-18.1.6.src_x86_baremetal.patch: PS7: > Oh, well, aborted my unpatched build after 4 hours :D yeah, the build times are crazy since version 18. -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Aug 2024 21:08:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[L] Change in coreboot[main]: dsm:dsm test [not to merge]. To test
by Poornima Tom (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Poornima Tom. Hello Poornima Tom, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84096?usp=email to look at the new patch set (#12). Change subject: dsm:dsm test [not to merge]. To test ...................................................................... dsm:dsm test [not to merge]. To test Change-Id: I979ddb5a9993a491ea48edaaf2a5ad2653430799 Signed-off-by: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 42 insertions(+), 247 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84096/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I979ddb5a9993a491ea48edaaf2a5ad2653430799 Gerrit-Change-Number: 84096 Gerrit-PatchSet: 12 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com>

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Nico Huber (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Arthur Heymans, Felix Singer, Martin L Roth. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84032?usp=email ) Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File util/crossgcc/patches/clang-18.1.6.src_x86_baremetal.patch: PS7: > Done Oh, well, aborted my unpatched build after 4 hours :D -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Aug 2024 20:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 funcions
by Cliff Huang (Code Review) 27 Aug '24

27 Aug '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 funcions ...................................................................... soc/intel/common/block/pmc: Add GPE1 funcions - Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag. - The existing static gpe functions has been renamed with ppe0. - Add gpe1 functions. BUG=362310295 TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT, and check if GPE1 sts bits have been printed during boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fd61489..b77d236 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -214,6 +214,16 @@ */ const char *const *soc_std_gpe_sts_array(size_t *a); + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) +/* + * This function returns array of string which represents + * names for the STD GPE1 status register bits. + * Size of the array is returned as an output parameter. + */ +const char *const *soc_std_gpe1_sts_array(int idx, size_t *a); +#endif + /* * This function gets the gpe0 dwX values from devicetree * for pmc_gpe_init which will use those to set the GPE_CFG diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 7650fe4..7da62a8 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -320,7 +320,7 @@ } /* Clear the gpio gpe0 status bits in ACPI registers */ -static void pmc_clear_gpi_gpe_status(void) +static void pmc_clear_gpi_gpe0_status(void) { int i; @@ -333,14 +333,14 @@ } } -static uint32_t reset_std_gpe_status(void) +static uint32_t reset_std_gpe0_status(void) { uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); return gpe_sts; } -static uint32_t print_std_gpe_sts(uint32_t gpe_sts) +static uint32_t print_std_gpe0_sts(uint32_t gpe_sts) { size_t array_size; const char *const *sts_arr; @@ -357,15 +357,53 @@ return gpe_sts; } -static void pmc_clear_std_gpe_status(void) +static void pmc_clear_std_gpe0_status(void) { - print_std_gpe_sts(reset_std_gpe_status()); + print_std_gpe0_sts(reset_std_gpe0_status()); } + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) +/* Clear the gpio gpe1 status bits in ACPI registers */ +static void pmc_clear_gpi_gpe1_status(void) +{ + int i; + + for (i = 0; i < GPE1_REG_MAX; i++) { + uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE1_STS(i)); + outl(gpe_sts, ACPI_BASE_ADDRESS + GPE1_STS(i)); + } +} + +static void print_std_gpe1_sts(void) +{ + size_t array_size; + const char *const *sts_arr; + int i; + + for (i = 0; i < GPE1_REG_MAX; i++) { + uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE1_STS(i)); + sts_arr = soc_std_gpe1_sts_array(i, &array_size); + printk(BIOS_DEBUG, "GPE1 STD STS[%d]: ", i); + print_num_status_bits(array_size, gpe_sts, sts_arr); + } + printk(BIOS_DEBUG, "\n"); +} + +static void pmc_clear_std_gpe1_status(void) +{ + print_std_gpe1_sts(); + pmc_clear_gpi_gpe1_status(); +} +#endif + void pmc_clear_all_gpe_status(void) { - pmc_clear_std_gpe_status(); - pmc_clear_gpi_gpe_status(); + pmc_clear_std_gpe0_status(); +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) + pmc_clear_std_gpe1_status(); +#endif + pmc_clear_gpi_gpe0_status(); } __weak -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Arthur Heymans (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Felix Singer, Martin L Roth, Nico Huber. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84032?usp=email ) Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... Patch Set 8: (1 comment) File util/crossgcc/patches/clang-18.1.6.src_x86_baremetal.patch: PS7: > We use clang 18.1.8 now. The file name needs to be adjusted. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 19:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Arthur Heymans (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Nico Huber. Hello Martin L Roth, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84032?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... util/crossgcc: Patch clang to enable linking x86 bare metal targets This allows clang to link x86 bare metal targets. TESTED: Qemu i440fx and q35 boot to payload with both 32 and 64bit code compiled with clang and LTO enabled with updated linker script. Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84032/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: util/crossgcc: Patch clang to enable linking x86 bare metal targets
by Felix Singer (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Arthur Heymans, Martin L Roth. Felix Singer has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84032?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/crossgcc: Patch clang to enable linking x86 bare metal targets ...................................................................... Patch Set 7: (1 comment) File util/crossgcc/patches/clang-18.1.6.src_x86_baremetal.patch: PS7: We use clang 18.1.8 now. The file name needs to be adjusted. -- To view, visit https://review.coreboot.org/c/coreboot/+/84032?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I943215c8714e392e52ea35667f2bf21e517c4255 Gerrit-Change-Number: 84032 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Aug 2024 19:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Maxim (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Angel Pons, Nicholas Sudsgaard. Maxim has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/84101?usp=email ) Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... Patch Set 2: (1 comment) File util/hda-decoder/main.go: https://review.coreboot.org/c/coreboot/+/84101/comment/5963bfbc_59c3eacd?us… : PS1, Line 85: } > Log that something went wrong? […] Agree, it looks like a compromise. Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 18:47:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Maxim (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Angel Pons, Maxim, Nicholas Sudsgaard. Hello Angel Pons, Nicholas Sudsgaard, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84101?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... util/hda-decoder: Protect 'fields' slice if empty string This avoids panic if the file contains an empty string or an incorrect configuration: goroutine 1 [running]: main.decodeFile({0x7ffd63da92a0?, 0xc000014070?}, 0x8?) /path/to/coreboot/util/hda-decoder/main.go:72 +0x2ef main.main() /path/to/coreboot/util/hda-decoder/main.go:158 +0x2a5 Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/hda-decoder/main.go 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84101/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>

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coreboot-gerrit August 2024