coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 27 Aug '24

27 Aug '24

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 36b47a3..2404ddf 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -76,4 +76,10 @@ Define the slp_s0_residency frequency to be reported in the LPIT ACPI table. +config SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 + bool "Include GPE1" + help + Include GPE1 STS and EN registers in FADT. + Requires define GPE1_STS(0) and GPE1_REG_MAX from the SOC header. + endif diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 1faf433..bb31086 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -107,6 +107,11 @@ /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) + fadt->gpe1_blk = pmbase + GPE1_STS(0); + fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t); + fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8; +#endif fill_fadt_extended_pm_io(fadt); fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 55: (24 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/c9d9de06_b89fb271?us… : PS55, Line 124: printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); shouldn't we return when we have detected a NULL pointer? you have identified a NULL pointer and next line#126, you have de-refer to fetch `s0ix_enable`. how is that possible ? additionally, this is single line statement hence, you don't need brace around https://review.coreboot.org/c/coreboot/+/83798/comment/0dafd437_dea832ff?us… : PS55, Line 148: } same https://review.coreboot.org/c/coreboot/+/83798/comment/fe8b4de5_4a960d79?us… : PS55, Line 161: } same https://review.coreboot.org/c/coreboot/+/83798/comment/f0ee9690_b744f1f3?us… : PS55, Line 233: vtd_engine_enabled this looks like a `bool` value that meant to check if VTD is enabled or not ? if yes, then perform below logic ``` const bool vtd_engine_enabled = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; ``` https://review.coreboot.org/c/coreboot/+/83798/comment/f57f8c40_72b287e2?us… : PS55, Line 235: DEBUG_WILL what you mean by `DEBUG_WILL` is this kind of macro ? https://review.coreboot.org/c/coreboot/+/83798/comment/3a5486e0_a381243b?us… : PS55, Line 238: PCI_DEVFN_IGD we kept IGD default enabled. does this still make sense ? https://review.coreboot.org/c/coreboot/+/83798/comment/8cee8b95_2fe1eb28?us… : PS55, Line 238: 0x1 are you checking BIT0? if yes, then what BIT-0 refers to here ? refer to my feedback above https://review.coreboot.org/c/coreboot/+/83798/comment/ce159de4_51d6046b?us… : PS55, Line 240: DEBUG_WILL same? https://review.coreboot.org/c/coreboot/+/83798/comment/512fe5ab_5547ec5d?us… : PS55, Line 241: GFXVT_BASE_ADDRESS why are you not passing `MCHBAR32(GFXVTBAR)` aka gfxvtbar https://review.coreboot.org/c/coreboot/+/83798/comment/4d4ab024_f922bcfd?us… : PS55, Line 247: (is_devfn_enabled(PCI_DEVFN_DPTF) || : is_devfn_enabled(PCI_DEVFN_IPU) || : is_devfn_enabled(PCI_DEVFN_NPU) || : is_devfn_enabled(PCI_DEVFN_IAA)) why we need to check these logic twice? one here and one at line#258-#265? just once makes sense to me. Just check if BIT(1) is set? https://review.coreboot.org/c/coreboot/+/83798/comment/0b455056_a96ff997?us… : PS55, Line 251: 0x2 what is BIT(1)? need macro https://review.coreboot.org/c/coreboot/+/83798/comment/e6002d46_02edef40?us… : PS55, Line 330: 0x7 what is this magic value ? can you please explain? https://review.coreboot.org/c/coreboot/+/83798/comment/121f4e90_a0ecc353?us… : PS55, Line 347: } why using NULL pointer w/o returning? File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/8330a623_a98ee3f4?us… : PS55, Line 46: PTL_U_404_4_15W_CORE, /* 4 P-cores +0 E-cores + 4 LP E-cores + 4Xe25W*/ one space after `+` https://review.coreboot.org/c/coreboot/+/83798/comment/20e53648_6cb5ac17?us… : PS55, Line 46: 4Xe25W this is 25W? https://review.coreboot.org/c/coreboot/+/83798/comment/a770c792_1b886a77?us… : PS55, Line 49: PTL_H_484_45W_CORE n https://review.coreboot.org/c/coreboot/+/83798/comment/b72a63b6_71bb9759?us… : PS55, Line 68: PCI_DID_INTEL_PTL_H_ID_2 as per EDS this is 45W SOC part bt you have added this as 25W SKU File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/9f2b3d0b_38b5af58?us… : PS50, Line 43: PTL_U_404_15W_CORE, : PTL_H_484_25W_CORE, : PTL_H_484_45W_CORE, > Hi Subrata, 404 means =(4 P-cores +0 E-cores + 4 LP > E-cores) & 484 mean =(4 P-cores +8 E-cores + 4 LP Ecores). > > Is it Ok to carry forwaed this naming? > About keeping comment, i have add them. Please let me know if this works. please add those details as part of the comment then only have such magic numbers in macro name else drop it. File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/5596a056_46458902?us… : PS55, Line 167: } same , please return if NULL https://review.coreboot.org/c/coreboot/+/83798/comment/ef43637c_9d770b1a?us… : PS55, Line 256: soc pcd as well ? File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/0d8a3287_a6f36046?us… : PS55, Line 129: } same https://review.coreboot.org/c/coreboot/+/83798/comment/810ca143_b850e8ae?us… : PS55, Line 171: } same File src/soc/intel/pantherlake/include/soc/p2sb.h: https://review.coreboot.org/c/coreboot/+/83798/comment/15acc40a_c3d7b30b?us… : PS55, Line 12: soc_ pcd File src/soc/intel/pantherlake/p2sb.c: https://review.coreboot.org/c/coreboot/+/83798/comment/889ff557_bca7a431?us… : PS55, Line 47: soc_ pcd -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 55 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 18:16:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Karthik Ramasubramanian (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Karthik Ramasubramanian has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 15: (8 comments) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/4d472271_bbaca9e4?us… : PS11, Line 15: #define SET_PSYSPL2(e, w) ((e) * (w) / 100) > We only have lotso board - I can test it there […] Acknowledged. Let us update Brox for now. Once all the variant usages are removed, we can remove it. https://review.coreboot.org/c/coreboot/+/83752/comment/6bfd346a_dd95a4d3?us… : PS11, Line 16: SET_PL2 > Other variant's build were failing - just to make sure other variants are not affected i added this […] Acknowledged. Let us update Brox for now. Once all the variant usages are removed, we can remove it. https://review.coreboot.org/c/coreboot/+/83752/comment/a7ce42ad_893844e8?us… : PS11, Line 146: void variant_update_psys_power_limits > Other variant's build were failing - just to make sure other variants are not affected i added this […] Acknowledged File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/e517df42_1fd43d9e?us… : PS15, Line 64: 35 I think with 32% efficiency it is 35 W. But for charger rating >= 60 W, the code is using 36% efficiency (39 Watts). Do you want it to be 32% efficiency or 36% efficiency? https://review.coreboot.org/c/coreboot/+/83752/comment/43228663_d31ad1d4?us… : PS15, Line 67: Nit: Remove this extra line. https://review.coreboot.org/c/coreboot/+/83752/comment/ba46c483_2b042ede?us… : PS15, Line 90: CONFIG(EC_GOOGLE_CHROMEEC) This will be true for all the Google Mainboard even in fatcat (@subrata to confirm) and hence can be removed. https://review.coreboot.org/c/coreboot/+/83752/comment/a2ad9e79_6cf76430?us… : PS15, Line 106: Adapter is not connected Power limit not updated because USB Type-C charger is not detected. File src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/83752/comment/fc51cb35_ac8a2238?us… : PS15, Line 11: #define FSPM_MAX_NONTURBO_FREQ 0x1 Please define this in src/soc/intel/alderlake/chip.h. This belongs there. Also define all the values that this UPD can take as an enum. -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 15 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 16:55:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 48: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83789/comment/4235529d_0a4e6d52?us… : PS47, Line 10: supporting ACPI ASL > Written from scratch, or copied from somewhere? will make the change in the next patchset. https://review.coreboot.org/c/coreboot/+/83789/comment/79371ff9_31052aae?us… : PS47, Line 21: Verified > How? will add more info in the next patchset. -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 48 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Aug 2024 16:41:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Cliff Huang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 48: (2 comments) Patchset: PS47: > Don't you need to rebase this CL on top of CB:83997 Done File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83789/comment/89a356c4_5674b3dd?us… : PS17, Line 263: Since Lunarlake, OS pinctrl no long provides SOC GPIO pincntrl info. : Rather, firmware is responsible for providing such info via APCI. : Firmware can provide entire PADs or excluding those non GPP_[group]_[number] : at the end of each community. > > Our gpio pinctrl owner points me this link. https://intelpedia.intel. […] I am asking for the external document for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 48 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Aug 2024 16:35:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick
by Subrata Banik (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, Simon Yang. Subrata Banik has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/84098?usp=email ) Change subject: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Gerrit-Change-Number: 84098 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 16:07:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick
by Simon Yang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, Subrata Banik. Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/84098?usp=email ) Change subject: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick ...................................................................... Patch Set 8: (4 comments) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/84098/comment/e7e8a007_fc1d06fc?us… : PS7, Line 13: TRANS_DDI_AUDIO_MUTE_OVERRIDE_MASK > u don't need this anymore I just don't think they are the same meaning so keep it. https://review.coreboot.org/c/coreboot/+/84098/comment/0909a9f3_e5ec0f82?us… : PS7, Line 14: TRANS_DDI_AUDIO_MUTE_OVERRIDE_AND_SET > can you please rename this now […] Done https://review.coreboot.org/c/coreboot/+/84098/comment/2729e8b4_1d3dfa19?us… : PS7, Line 57: TRANS_DDI_AUDIO_MUTE_OVERRIDE_MASK > TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS Done https://review.coreboot.org/c/coreboot/+/84098/comment/92061ef9_432dedfd?us… : PS7, Line 58: TRANS_DDI_AUDIO_MUTE_OVERRIDE_AND_SET > TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Gerrit-Change-Number: 84098 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 15:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick
by Simon Yang (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, Simon Yang. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84098?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick ...................................................................... mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG:b=357764688 BRANCH=firmware-nissa-15217.B TEST:Verfied on Anraggar and cannot reproduce the issue Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/mainboard/google/brya/variants/anraggar/variant.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84098/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Gerrit-Change-Number: 84098 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick
by Subrata Banik (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, Simon Yang. Subrata Banik has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/84098?usp=email ) Change subject: mb/google/nissa/var/anraggar: Force audio mute to avoid screen flick ...................................................................... Patch Set 7: (4 comments) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/84098/comment/eff3ba43_3798af6e?us… : PS7, Line 13: TRANS_DDI_AUDIO_MUTE_OVERRIDE_MASK u don't need this anymore https://review.coreboot.org/c/coreboot/+/84098/comment/89a975b6_479d959e?us… : PS7, Line 14: TRANS_DDI_AUDIO_MUTE_OVERRIDE_AND_SET can you please rename this now ``` TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS ``` https://review.coreboot.org/c/coreboot/+/84098/comment/beee2f48_3b0174b5?us… : PS7, Line 57: TRANS_DDI_AUDIO_MUTE_OVERRIDE_MASK TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS https://review.coreboot.org/c/coreboot/+/84098/comment/b08ece69_dd262b65?us… : PS7, Line 58: TRANS_DDI_AUDIO_MUTE_OVERRIDE_AND_SET TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS -- To view, visit https://review.coreboot.org/c/coreboot/+/84098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Gerrit-Change-Number: 84098 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Aug 2024 15:42:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
by Dinesh Gehlot (Code Review) 27 Aug '24

27 Aug '24

Attention is currently required from: Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, V Sowmya. Dinesh Gehlot has posted comments on this change by V Sowmya. ( https://review.coreboot.org/c/coreboot/+/84019?usp=email ) Change subject: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d Gerrit-Change-Number: 84019 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 27 Aug 2024 15:23:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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