coreboot-gerrit August 2024

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[M] Change in coreboot[main]: soc/mediatek/mt8196: add unmask eint event for bootblock
by Yidi Lin (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: add unmask eint event for bootblock ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84025/comment/cb393645_eba6fe2a?us… : PS8, Line 7: add Add -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:55:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Maxim. Nicholas Sudsgaard has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/84101?usp=email ) Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... Patch Set 2: (1 comment) File util/hda-decoder/main.go: https://review.coreboot.org/c/coreboot/+/84101/comment/300b2a07_08b6a0e4?us… : PS2, Line 73: Something went wrong > Yes, the error handling isn't great, but let's not forget that the point of this change is to fix a […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:53:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Angel Pons, Nicholas Chin. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80411?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Patch Set 24: (1 comment) File Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg: PS22: > I would go by file size rather than resolution Reduced the image size to ~83K by using `convert in.jpg -quality 35% -resize 800x800 out.jpg`. I think this gives the best quality-size ratio. I agree with Angel here. If the resolution issue is fixed, maybe we should update the rules (max 128K?). -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 24 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:50:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Angel Pons, Nicholas Chin, Nicholas Sudsgaard. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80411?usp=email to look at the new patch set (#23). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 3 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 23 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Angel Pons (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Maxim, Nicholas Sudsgaard. Angel Pons has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/84101?usp=email ) Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... Patch Set 2: (1 comment) File util/hda-decoder/main.go: https://review.coreboot.org/c/coreboot/+/84101/comment/a8b4b833_b17b3a2d?us… : PS2, Line 73: Something went wrong > Let's be a little bit more descriptive than that. […] Yes, the error handling isn't great, but let's not forget that the point of this change is to fix a crash/panic. I would prefer to get it submitted as-is into the coreboot release (IIRC it's going to happen soon). The error message can be improved in a follow-up change. I would consider logging the output of `scanner.Text()` for example (best discussed in a follow-up). -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:41:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[L] Change in coreboot[main]: mb/lattepanda: Add support for LattePanda Mu
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Felix Held, KunYi Chen, Martin L Roth, Nicholas Chin, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by KunYi Chen. ( https://review.coreboot.org/c/coreboot/+/83719?usp=email ) Change subject: mb/lattepanda: Add support for LattePanda Mu ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Gerrit-Change-Number: 83719 Gerrit-PatchSet: 10 Gerrit-Owner: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: KunYi Chen <kunyi.chen(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:26:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Derek Huang (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Derek Huang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 01:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/hda-decoder: Protect 'fields' slice if empty string
by Nicholas Sudsgaard (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Maxim. Nicholas Sudsgaard has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/84101?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/hda-decoder: Protect 'fields' slice if empty string ...................................................................... Patch Set 2: (1 comment) File util/hda-decoder/main.go: https://review.coreboot.org/c/coreboot/+/84101/comment/b7fb9983_f47d0826?us… : PS2, Line 73: Something went wrong Let's be a little bit more descriptive than that. Also, I would not make that a comment, I want to prevent anyone from accidentally copy-pasting the output with errors by making it not compile. ```suggestion fmt.Println("[ERROR] Failed to parse: expected exactly 2 arguments") ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ae8544e52d82e8d8a82a88a85a2de7d2f295ec1 Gerrit-Change-Number: 84101 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 00:44:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: tree: Use boolean for "eist_enable"
by Elyes Haouas (Code Review) 28 Aug '24

28 Aug '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83575?usp=email ) Change subject: tree: Use boolean for "eist_enable" ...................................................................... tree: Use boolean for "eist_enable" Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 45 files changed, 48 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved Jonathon Hall: Looks good to me, but someone else must approve Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a33ee18..e489e25 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 8999aa3..21661f9 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -36,7 +36,7 @@ subsystemid 0x1025 0x1037 inherit device ref system_agent on # Enable "Enhanced Intel SpeedStep" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 97C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 92e4ba7..59e297c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -4,7 +4,7 @@ register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index f078cdf..11a8749 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -17,7 +17,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index bb896aa..ac4ec46 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -16,7 +16,7 @@ # FSP Configuration register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 7330862..ad735ed 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -19,7 +19,7 @@ register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" # "Intel SpeedStep Technology" - register "eist_enable" = "1" + register "eist_enable" = "true" # DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index db843f5..c0779c6 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -19,7 +19,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25b8d9f..2976deb 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Mapping of USB port # to device #+----------------+-------+-----------------------------------+ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f94e93..97b0c20 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -10,7 +10,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 74780d0..3b07bf7 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -5,7 +5,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ }" - register "eist_enable" = "1" + register "eist_enable" = "true" device domain 0 on subsystemid 0x103c 0x2b5e inherit diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index e6655b5..51d3b26 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -6,7 +6,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9599cec..4f7d7eb 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -7,7 +7,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index d7d83cd..e874679 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index cfe6b50..738c8a3 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index bc000c7..317de80 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -108,7 +108,7 @@ register "s0ix_enable" = "0" # Enable Turbo - register "eist_enable" = "1" + register "eist_enable" = "true" register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 14e6048..01c5df7 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937..df0dbdf 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ }" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502..9b0357f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "eist_enable" = "1" + register "eist_enable" = "true" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index cc1433d..dfacdea 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index c992c4f..f8e494a 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake - register "eist_enable" = "1" + register "eist_enable" = "true" register "s0ix_enable" = "0" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 80c497b..e26e6b2 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -21,7 +21,7 @@ register "s0ix_enable" = "0" - register "eist_enable" = "1" + register "eist_enable" = "true" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 01ae0f2..5b448f9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -18,7 +18,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index d386397..311d96c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -5,7 +5,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index f709664..a555394 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -15,7 +15,7 @@ register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 81d593f..df8bd99 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 08f5006..87ccb8a 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 26197a2..1144162 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # Not used but timings left for reference diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 2a4a21a..f5b7a1f 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 81b023c..4e27318 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index dee0bf5..3a99ab4 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index aaffd4e..ed0a520 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index ba88a71..5760e66 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index e4658a7..9251440 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 4eea043..cc3c619 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c198ea9..7e3ef0c 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 25ba3a6..dd4d597 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 58a4fcf..2bda9dc 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -12,7 +12,7 @@ # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # CPU (soc/intel/tigerlake/cpu.c) # Power limits diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d7a527a..d96249d 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -12,7 +12,7 @@ # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable s0ix, required for TGL-U register "s0ix_enable" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 53d5943..1c5d720 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -18,7 +18,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a490540..b58b244 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -467,7 +467,7 @@ bool skip_ext_gfx_scan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 1e7e5a5..97657e2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,7 +237,7 @@ /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5330f22..e5c7f54 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -258,8 +258,8 @@ uint8_t Heci2Enable; uint8_t Heci3Enable; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + /* Enable/Disable EIST. true:Enabled, false:Disabled */ + bool eist_enable; /* * SerialIO device mode selection: diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f8d069e..542ccb6 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -178,7 +178,7 @@ /* Gfx related */ bool SkipExtGfxScan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 7997f7d..4e0ba86 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -459,8 +459,8 @@ u8 SlowSlewRateForSa; /* Enable/Disable EIST - * 1b - Enabled - * 0b - Disabled + * true - Enabled + * false - Disabled */ bool eist_enable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f8d4d49..e8d417e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -286,8 +286,8 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + /* Enable/Disable EIST. true:Enabled, false:Disabled */ + bool eist_enable; /* Enable C6 DRAM */ uint8_t enable_c6dram; -- To view, visit https://review.coreboot.org/c/coreboot/+/83575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Gerrit-Change-Number: 83575 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 28 Aug '24

28 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/4b8acf1f_39288a80?us… : PS2, Line 113: /* NOTE: gpe1 is after gpe0, where has _STS an _EN set. base unit: bit. */ > Maybe you should change this to […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 28 Aug 2024 00:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hannah Williams <hannah.williams(a)intel.com>

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