coreboot-gerrit August 2024

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[S] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Saurabh Mishra (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Felix Held, Paul Menzel, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 33: (1 comment) Patchset: PS31: > your code is still not buildable. […] I am working on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 33 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Aug 2024 12:04:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/orisa: Update ISH GPIO's configuration
by Varun Upadhyay (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Deepti Deshatty, Dinesh Gehlot, Eric Lai, Kapil Porwal, Li Feng, Li1 Feng, Nick Vaccaro, Rishika Raj, Subrata Banik, V Sowmya. Hello Deepti Deshatty, Dinesh Gehlot, Eric Lai, Kapil Porwal, Li Feng, Li1 Feng, Nick Vaccaro, Rishika Raj, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83656?usp=email to look at the new patch set (#4). Change subject: mb/google/trulo/var/orisa: Update ISH GPIO's configuration ...................................................................... mb/google/trulo/var/orisa: Update ISH GPIO's configuration This patch configures the GPIO pins to enable ISH on the Orisa device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/orisa. Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> --- M src/mainboard/google/brya/variants/orisa/gpio.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83656/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Gerrit-Change-Number: 83656 Gerrit-PatchSet: 4 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com>

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[L] Change in coreboot[main]: vc/intel/fsp2_0: Add Skeleton FSP header for PTL
by Saurabh Mishra (Code Review) 01 Aug '24

01 Aug '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email ) Change subject: vc/intel/fsp2_0: Add Skeleton FSP header for PTL ...................................................................... vc/intel/fsp2_0: Add Skeleton FSP header for PTL Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h 6 files changed, 511 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83732/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h new file mode 100644 index 0000000..466cb8e --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h @@ -0,0 +1,55 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.p… + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include <IndustryStandard/SmBios.h> + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h new file mode 100644 index 0000000..831fd92 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h @@ -0,0 +1,99 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 2023 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include <Guid/FspHeaderFile.h> + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h new file mode 100644 index 0000000..9661285 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5450 /* 'PTLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5450 /* 'PTLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5450 /* 'PTLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h new file mode 100644 index 0000000..76c03f7 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** FSP M Configuration +**/ +typedef struct { + + /* Placeholder for FSP_M_CONFIG UPDs */ + +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH2_UPD FspmArchUpd; + +/** Offset 0x0060 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace4[6]; + +/** Offset 0x0066 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h new file mode 100644 index 0000000..c10ec84 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h @@ -0,0 +1,96 @@ +/** @file + +Copyright (c) 2024, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +/** FSP S Configuration +**/ +typedef struct { + + /* Placeholder for FSP_S_CONFIG UPDs */ + +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH2_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0040 +**/ + UINT8 UnusedUpdSpace1[6]; + +/** Offset 0x0046 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h new file mode 100644 index 0000000..5f5209a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h @@ -0,0 +1,124 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + INTEL CONFIDENTIAL + Copyright (C) 1999 Intel Corporation. + + This software and the related documents are Intel copyrighted materials, + and your use of them is governed by the express license under which they + were provided to you ("License"). Unless the License provides otherwise, + you may not use, modify, copy, publish, distribute, disclose or transmit + this software or the related documents without Intel's prior written + permission. + + This software and the related documents are provided as is, with no + express or implied warranties, other than those that are expressly stated + in the License. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +/** + Memory Info Data Hob +**/ +typedef struct { +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob +**/ +typedef struct { +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/83732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Gerrit-Change-Number: 83732 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Use FSP MP Init by default when INTEL_TXT enabled
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83731?usp=email ) Change subject: soc/intel/cannonlake: Use FSP MP Init by default when INTEL_TXT enabled ...................................................................... soc/intel/cannonlake: Use FSP MP Init by default when INTEL_TXT enabled To get all CPU features programmed properly for Intel TXT we need to use FSP MP Init. Have not yet found a way to program the features correctly and not have the FSP lock the registers before coreboot can do something about it. TEST=Boot Linux with tboot on Protectli VP4670 with TXT enabled Change-Id: I0f57e97477b89d953e24d0657335b777f4eaa45d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83731/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 3aa06f4..cc04929 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -340,6 +340,13 @@ hex default 0x40000 # 256KB +# To get all CPU features programmed properly for Intel TXT we need +# to use FSP MP Init. Have not yet found a way to program the features +# correctly and not have the FSP lock the registers before coreboot +# can do something about it. +config USE_INTEL_FSP_MP_INIT + default y if INTEL_TXT + config INTEL_GMA_BCLV_OFFSET default 0xc8258 -- To view, visit https://review.coreboot.org/c/coreboot/+/83731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f57e97477b89d953e24d0657335b777f4eaa45d Gerrit-Change-Number: 83731 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot program MSR_IA32_DEBUG_INTERFACE
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot program MSR_IA32_DEBUG_INTERFACE ...................................................................... soc/intel/cannonlake: Let coreboot program MSR_IA32_DEBUG_INTERFACE Intel TXT requires the debug interface to be disabled. There is no way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so let coreboot handle it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/lockdown.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83730/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cdf8fda..502cc3b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -678,6 +678,15 @@ */ params->SpiFlashCfgLockDown = lockdown_by_fsp; #endif + /* + * IA32_DEBUG_INTERFACE_MSR has to be locked by coreboot, + * because FSP does not do it unless DebugInterfaceEnable is 1. + * But to use Intel TXT, the debug interface has to be disabled, + * so let coreboot handle the IA32_DEBUG_INTERFACE_MSR programming. + */ + supd->FspsConfig.DebugInterfaceEnable = 0; + supd->FspsTestConfig.DebugInterfaceEnable = 0; + supd->FspsTestConfig.DebugInterfaceLockEnable = 0; #if !CONFIG(SOC_INTEL_COMETLAKE) params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 3205c7f..ff8842e 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -1,11 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/msr.h> #include <device/mmio.h> #include <intelblocks/cfg.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pm.h> +#define MSR_IA32_DEBUG_INTERFACE 0xc80 +#define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) +#define MSR_IA32_DEBUG_INTERFACE_LOCK (1 << 30) + +static void cpu_lockdown_cfg(void) +{ + msr_t msr = rdmsr(MSR_IA32_DEBUG_INTERFACE); + + if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { + if (CONFIG(INTEL_TXT)) + msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN; + + msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK; + wrmsr(MSR_IA32_DEBUG_INTERFACE, msr); + } +} + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -59,4 +77,5 @@ { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + cpu_lockdown_cfg(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[XS] Change in coreboot[main]: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83729?usp=email ) Change subject: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage ...................................................................... soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage Call intel_txt_romstage_init to let coreboot have control over as much initialization as possible. The function will also call the BIOS ACM SCLEAN if necessary. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled. Change-Id: I5a667f2bb2d4fa658b4dafb556289021649dc0e0 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83729/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index b3777b6..d586305 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -9,6 +9,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/smbus.h> #include <memory_info.h> +#include <security/intel/txt/txt.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -130,6 +131,10 @@ cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) { -- To view, visit https://review.coreboot.org/c/coreboot/+/83729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a667f2bb2d4fa658b4dafb556289021649dc0e0 Gerrit-Change-Number: 83729 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake,skylake: Fix locking SMRAM
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83728?usp=email ) Change subject: soc/intel/cannonlake,skylake: Fix locking SMRAM ...................................................................... soc/intel/cannonlake,skylake: Fix locking SMRAM Intel TXT SINIT required the D_LCK bit set. Although coreboot tries to set it, the bit ws still clear. The D_LCK bit has to be set using I/O CF8/CFC cycle. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/skylake/cpu.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83728/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index b8a2c8c..53757f5 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -162,14 +162,14 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can - * make the SMM registers writable again. + * make the SMM registers writable again. D_LCK bit + * requires the PCI 0xcf8/0xcfc I/O access. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } static void post_mp_init(void) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5cf48ea..057aece 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -164,14 +164,14 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can - * make the SMM registers writable again. + * make the SMM registers writable again. D_LCK bit + * requires the PCI 0xcf8/0xcfc I/O access. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } static void vmx_configure(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/83728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c Gerrit-Change-Number: 83728 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83727?usp=email ) Change subject: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs ...................................................................... soc/intel/cannonlake: Hook up Intel TXT FSP UPDs Set necessary parameters so that FSP can call BIOS ACM ACHECK after MRC. It is required to perform ACHECK in certain conditions and the Intel TXT will not function properly without calling it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled. Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83727/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index e1eede2..cdf8fda 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -687,6 +687,8 @@ params->PavpEnable = CONFIG(PAVP); + params->TxtEnable = CONFIG(INTEL_TXT); + /* * Prevent FSP from programming write-once subsystem IDs by providing * a custom SSID table. Must have at least one entry for the FSP to diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 2b25285..860e3cb 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -133,6 +133,26 @@ /* Set HECI1 PCI BAR address */ m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS; +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + /* FSP will need the BIOS ACM to call ACHECK if necessary */ + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + m_cfg->TxtImplemented = 1; + m_cfg->Txt = 1; + m_cfg->SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + m_cfg->TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + m_cfg->TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + /* Set DPR base to non-zero, FSP will update it internally in MRC */ + m_cfg->TxtDprMemoryBase = 1; + m_cfg->BiosAcmBase = acm_base; + m_cfg->BiosAcmSize = acm_size; + m_cfg->ApStartupBase = 1; /* Set to non-zero, FSP does NULL check */ +#endif + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d Gerrit-Change-Number: 83727 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[XS] Change in coreboot[main]: security/intel/txt: Restart APs after successful SCHECK
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Michał Żygowski, Paul Menzel. Michał Żygowski has uploaded a new patch set (#6) to the change originally created by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82697?usp=email ) Change subject: security/intel/txt: Restart APs after successful SCHECK ...................................................................... security/intel/txt: Restart APs after successful SCHECK When INTEL_TXT is enabled, the APs are stopped before a SCHECK call to ACM is invoked. However, SCHECK happens before the final MTRRs are programmed on APs. This results in MTRR programming failure on APs on platforms using INTEL_TXT. Restart the APs after SCHECK attempt to ensure the APs have their MTRRs programmed correctly. TEST=Run coreboot with INTEL_TXT enabled on Protectli VP4670 and see coreboot no longer complains on inability to run a MTRR programming task on APs. Change-Id: I8e013b1a75752e4f01cac7c1eb10d0430d48edf6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/intel/txt/ramstage.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/82697/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/82697?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e013b1a75752e4f01cac7c1eb10d0430d48edf6 Gerrit-Change-Number: 82697 Gerrit-PatchSet: 6 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: security/tpm: Add TPM2 NV_ReadPublic command support
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Christian Walter, Krystian Hebel, Michał Kopeć, Michał Żygowski. Michał Żygowski has uploaded a new patch set (#12) to the change originally created by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82037?usp=email ) Change subject: security/tpm: Add TPM2 NV_ReadPublic command support ...................................................................... security/tpm: Add TPM2 NV_ReadPublic command support Adds support for `tpm2_nvreadpublic`, which allows to read the public area and attributes of a TPM2 Non-Volatile (NV) index. The use case is to check for indices required by Intel TXT to avoid a reset loop caused by BIOS ACM SCHECK. TEST=Read Intel TXT TPM2 NV indices in Intel TXT driver. Change-Id: I3c032b4f88d445372beebbe354f458a061a63bb9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 153 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/82037/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/82037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c032b4f88d445372beebbe354f458a061a63bb9 Gerrit-Change-Number: 82037 Gerrit-PatchSet: 12 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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