coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymaps
by Felix Held (Code Review) 01 Aug '24

01 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83684?usp=email ) Change subject: acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymaps ...................................................................... acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymaps This patch supports keyboards that have delete key but without numpad. To prevent KEY_DELETE be defined twice, move it from numeric_keypad_keymaps to rest_of_keymaps. BUG=b:345231373 TEST=Build and test on Riven/Craaskino, delete key function works Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/acpi/acpigen_ps2_keybd.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified David Wu: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, approved diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 43a1ece..8691207 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -69,7 +69,6 @@ KEYMAP(0xc7, KEY_HOME), KEYMAP(0xcf, KEY_END), /* Row-1 */ - KEYMAP(0xd3, KEY_DELETE), KEYMAP(0xb5, KEY_KPSLASH), KEYMAP(0x37, KEY_KPASTERISK), KEYMAP(0x4a, KEY_KPMINUS), @@ -99,6 +98,7 @@ static uint32_t rest_of_keymaps[] = { /* Row-0 */ KEYMAP(0x01, KEY_ESC), + KEYMAP(0xd3, KEY_DELETE), /* Row-1 */ KEYMAP(0x29, KEY_GRAVE), KEYMAP(0x02, KEY_1), -- To view, visit https://review.coreboot.org/c/coreboot/+/83684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c Gerrit-Change-Number: 83684 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: security/tpm: Add TPM2 NV_ReadPublic command support
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Christian Walter, Filip Lewiński, Krystian Hebel, Michał Kopeć. Michał Żygowski has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82037?usp=email ) Change subject: security/tpm: Add TPM2 NV_ReadPublic command support ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: Not sure why PSP verstage build fails. Maybe one of the stack definitions is too small? src/soc/amd/picasso/include/soc/psp_verstage_addr.h -- To view, visit https://review.coreboot.org/c/coreboot/+/82037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c032b4f88d445372beebbe354f458a061a63bb9 Gerrit-Change-Number: 82037 Gerrit-PatchSet: 14 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 14:54:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/rpl: Set I2C0 speed to fast
by Paul Menzel (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83627?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/starlabs/starbook/rpl: Set I2C0 speed to fast ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83627/comment/2505914a_e5fb95cd?us… : PS2, Line 7: Set Increase or lower? https://review.coreboot.org/c/coreboot/+/83627/comment/ec2c18da_74e18031?us… : PS2, Line 11: What is the default speed? -- To view, visit https://review.coreboot.org/c/coreboot/+/83627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fdbd3124fca27fcd4dced81d8e2aa2f91fe4651 Gerrit-Change-Number: 83627 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 01 Aug 2024 14:23:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: security/intel/txt: Verify Intel TXT required TPM2 indices presence
by Filip Lewiński (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Filip Lewiński, Michał Żygowski. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82417?usp=email ) Change subject: security/intel/txt: Verify Intel TXT required TPM2 indices presence ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b4267b2d51e21cfa514e96301f30ebf7437c470 Gerrit-Change-Number: 82417 Gerrit-PatchSet: 8 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 14:15:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83734?usp=email ) Change subject: soc/intel/cannonlake: Set correct default sizes of Intel TXT memory ...................................................................... soc/intel/cannonlake: Set correct default sizes of Intel TXT memory The CoffeeLake/CometLake requires the SINIT to be 320KB and the heap of 960KB. The DPR should also be 4MB for these platforms. If these regions are too small, the SINIT complains with error class 5 major code 2 - insufficient HEAP size. TEST=Boot Linux with tboot on Protectli VP4670 with TXT enabled. Change-Id: I5340165579174eb8ab26dfaae452896d6646c900 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/83734/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cc04929..7976466 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -336,10 +336,22 @@ hex default 0xe00 +if INTEL_TXT + config INTEL_TXT_BIOSACM_ALIGNMENT - hex default 0x40000 # 256KB +config INTEL_TXT_DPR_SIZE + default 4 # 4MB + +config INTEL_TXT_SINIT_SIZE + default 0x50000 # 320KB + +config INTEL_TXT_HEAP_SIZE + default 0xf0000 # 960KB + +endif + # To get all CPU features programmed properly for Intel TXT we need # to use FSP MP Init. Have not yet found a way to program the features # correctly and not have the FSP lock the registers before coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/83734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5340165579174eb8ab26dfaae452896d6646c900 Gerrit-Change-Number: 83734 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: security/intel/txt: Make romstage init work on SOC_INTEL platforms
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Michał Kopeć, Michał Żygowski. Michał Żygowski has uploaded a new patch set (#4) to the change originally created by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82694?usp=email ) Change subject: security/intel/txt: Make romstage init work on SOC_INTEL platforms ...................................................................... security/intel/txt: Make romstage init work on SOC_INTEL platforms Use Intel SOC common PMC block to clear SLP_TYP field in ACPI PM1. It will enable the intel_txt_romstage_init to work on soc/skylake and soc/cannonlake. Newer SOCs like TigerLake already have CBnT and run ACM from FIT, so do not need to call intel_txt_romstage_init. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled. Change-Id: I892c9eff16d51adc94b75c9ef9f0f1be4f50bada Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/intel/txt/romstage.c 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82694/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82694?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I892c9eff16d51adc94b75c9ef9f0f1be4f50bada Gerrit-Change-Number: 82694 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XS] Change in coreboot[main]: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage
by Michał Żygowski (Code Review) 01 Aug '24

01 Aug '24

Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83729?usp=email ) Change subject: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage ...................................................................... soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage Call intel_txt_romstage_init to let coreboot have control over as much initialization as possible. The function will also call the BIOS ACM SCLEAN if necessary. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled. Change-Id: I5a667f2bb2d4fa658b4dafb556289021649dc0e0 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83729/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a667f2bb2d4fa658b4dafb556289021649dc0e0 Gerrit-Change-Number: 83729 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: i2c/drivers/generic: Return ROTM in a package
by Matt DeVillier (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83721?usp=email ) Change subject: i2c/drivers/generic: Return ROTM in a package ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Gerrit-Change-Number: 83721 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 01 Aug 2024 13:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/skyrim: Combine the function port_descriptors for variants
by Matt DeVillier (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Bao Zheng, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Paul Menzel, Zheng Bao. Matt DeVillier has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/83646?usp=email ) Change subject: mb/google/skyrim: Combine the function port_descriptors for variants ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/83646/comment/f6339a6e_b8f295d5?us… : PS5, Line 8: #if CONFIG(BOARD_GOOGLE_MARKARTH) || CONFIG(BOARD_GOOGLE_WINTERHOLD) I don't see a need to use a preprocessor define here. I'd also drop the enum and just create another DXIO descriptor for WLAN+NVME, and select that below vs replacing, but that's just me https://review.coreboot.org/c/coreboot/+/83646/comment/b29599b2_69b5fd92?us… : PS5, Line 38: #if CONFIG(BOARD_GOOGLE_MARKARTH) || CONFIG(BOARD_GOOGLE_WINTERHOLD) no preprocessor define - `if (CONFIG(BOARD_GOOGLE_MARKARTH) || CONFIG(BOARD_GOOGLE_WINTERHOLD)) {...}` will do just fine. You can also simplify it as: ``` if (MK or WH) { if (!EMMC_GPIO) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); emmc_dxio_descriptors[EMMC_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR; } else { printk(BIOS_DEBUG, "Defaulting to eMMC.\n"); } *dxio_descriptor = emmc_dxio_descriptors; *num = ARRAY_SIZE(emmc_dxio_descriptors); } else { *dxio_descriptor = skyrim_mdn_dxio_descriptors; *num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Gerrit-Change-Number: 83646 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 13:50:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: vc/intel/fsp2_0: Add Skeleton FSP header for PTL
by Saurabh Mishra (Code Review) 01 Aug '24

01 Aug '24

Attention is currently required from: Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email ) Change subject: vc/intel/fsp2_0: Add Skeleton FSP header for PTL ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Please run dos2unix […] Yes, i just was the reporting on Jenkins build. done. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/83732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Gerrit-Change-Number: 83732 Gerrit-PatchSet: 2 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 01 Aug 2024 13:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit August 2024