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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: vc/intel/fsp2_0: Add Skeleton FSP header for PTL
......................................................................
vc/intel/fsp2_0: Add Skeleton FSP header for PTL
Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
6 files changed, 511 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83732/2
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Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/83685?usp=email )
Change subject: security/vboot: Include new gbb flag to enforce CSE sync
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Marking this open.
Acknowledged
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Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83733?usp=email )
Change subject: Update vboot submodule to upstream main
......................................................................
Update vboot submodule to upstream main
Updating from commit id 4b12d392e5b1:
scripts: Add a script to convert a vbprivk to a PEM
to commit id f1f70f46dc54:
2lib: Add gbb flag to enforce CSE sync
-Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594
+Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2
Change-Id: I2c5b603ce5ea49e6c1aec293960184d84eedd1e7
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/83733/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 4b12d39..f1f70f4 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594
+Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83722?usp=email )
Change subject: mb/google/brya/var/orisa: Remove mux references from typec port
......................................................................
mb/google/brya/var/orisa: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/orisa/overridetree.cb
1 file changed, 1 insertion(+), 12 deletions(-)
Approvals:
build bot (Jenkins): Verified
Dinesh Gehlot: Looks good to me, approved
Eric Lai: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 0a58b3d..89d4d2f 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -519,21 +519,10 @@
device ref uart0 on end
device ref pch_espi on
chip ec/google/chromeec
- use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
- device ref pmc hidden
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port5 as usb2_port
- use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
- end
- end
- end
- end
+ device ref pmc hidden end
device ref hda on
chip drivers/sof
register "spkr_tplg" = "max98360a"
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Jonathon Hall has posted comments on this change by Jonathon Hall. ( https://review.coreboot.org/c/coreboot/+/83476?usp=email )
Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> I would have to ask "where would we stop?" If next time somebody runs into this […]
Ah I didn't realize this persisted through OS runtime, thanks Nico.
Is there somewhere we could allocate the Wuffs work area outside of the ordinary heap - where we wouldn't have this size limitation and it wouldn't persist through OS runtime? This work area isn't needed once the bootsplash is shown.
Do we have any infrastructure for allocating other available memory temporarily, or could we add it? (I can work on it, but I'd appreciate suggestions where to start if you have an idea.)
BTW, in combination with the issue address in patch 83475, this regression results in failure to boot if the bootsplash work area can't be allocated, where those bootsplashes worked on the older decoder.
PS2:
> NB. We should probably try to save the next person to run into this […]
It's not based on the file size, it's based on the image resolution + chroma subsampling, as I understand it. We would probably need to rely on ImageMagick being available at build time to figure that out. Or build the Wuffs decoder for the host and run it, maybe.
ImageMagick is already needed at build time if the bootsplash conversion is enabled in Kconfig, but it's not needed otherwise.
Either way this still has the heap cost during OS runtime that you mentioned, which I didn't realize. If we could use some other memory for the bootsplash, which we likely have, I think it'd address both problems, no static limitation and no runtime cost.
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Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63716?usp=email )
Change subject: [RFC]util/cbfstool: Rewrite trampoline in C
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS1:
> Is there another way to make it easier to chain load from other payloads?
Well I suppose you need to check if memory will overlap when loading one which I hope chainloaders do. So this is not an issue.
Patchset:
PS4:
> Are you still working on this, or should it be abandoned?
>
Not right now.
> What's the benefit to rewriting the code? The ASM has been tested and doesn't rely on GCC's interpretation of inline asm?
>
What's the benefit of coding in C rather than assembly? Also GCC is used for the assembly just as much as it is for inline assembly so I don't understand your argument about GCC interpretation of inline assembly. Making a 64bit version of this would trivial if it's compiled. Assembly would be pain.
> The ASM is well tested and doesn't really change much.
Then the same would apply to a C version.
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Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83671?usp=email )
Change subject: mb/google/trulo: support ISH
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83671/comment/97f88271_c8c719f6?us… :
PS2, Line 10: & Configure
> and configure
Done
https://review.coreboot.org/c/coreboot/+/83671/comment/ebc308c5_674f05e0?us… :
PS2, Line 9: Define ISH main firmware name so ISH shim loader can load firmware
: from file system & Configure GPIO for ISH
> Please add a dot/period at the end.
Done
https://review.coreboot.org/c/coreboot/+/83671/comment/ff5067bd_bceb0747?us… :
PS2, Line 11:
> What schematics version did you use?
Done
File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83671/comment/8be762d1_cd6492cf?us… :
PS2, Line 50: trulo_ish
> Let me check internally and come back.
Updated to a generic name ish_fw.bin
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Hello Deepti Deshatty, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Li1 Feng, Nick Vaccaro, Rishika Raj, Subrata Banik, V Sowmya, Yuval Peress, build bot (Jenkins),
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Change subject: mb/google/trulo: support ISH
......................................................................
mb/google/trulo: support ISH
Define ISH main firmware name so ISH shim loader can load firmware
from file system & configure GPIO for ISH in accordance
with schematic_20240607.
BUG=b:354607924
TEST=Boot trulo board, check that ISH is enabled and loaded
lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc
Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1
Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/mainboard/google/brya/variants/trulo/gpio.c
2 files changed, 11 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83671/3
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