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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#41).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/41
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Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83732/comment/7ee2f8bd_f9bc070a?us… :
PS4, Line 7: vc/intel/fsp2_0
> ``` […]
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/b4bafbf5_995fc549?us… :
PS4, Line 1: /** @file
: Intel Firmware Version Info (FVI) related definitions.
:
: @todo update document/spec reference
:
: Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
: SPDX-License-Identifier: BSD-2-Clause-Patent
:
: @par Specification Reference:
: System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
: http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.p…
:
: **/
> please use open source applicable copyright header
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/756e6931_2e62ad82?us… :
PS4, Line 13: @copyright
: INTEL CONFIDENTIAL
: Copyright (C) 2023 Intel Corporation.
:
: This software and the related documents are Intel copyrighted materials,
: and your use of them is governed by the express license under which they
: were provided to you ("License"). Unless the License provides otherwise,
: you may not use, modify, copy, publish, distribute, disclose or transmit
: this software or the related documents without Intel's prior written
: permission.
:
: This software and the related documents are provided as is, with no
: express or implied warranties, other than those that are expressly stated
: in the License.
> same
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/2160b2ed_ee965e91?us… :
PS4, Line 46:
> why empty lines?
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/71416b79_87ce97b2?us… :
PS4, Line 64:
> same as FSP-M
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/785549f8_8c6a08e1?us… :
PS4, Line 1: /** @file
: This file contains definitions required for creation of
: Memory S3 Save data, Memory Info data and Memory Platform
: data hobs.
:
: @copyright
: INTEL CONFIDENTIAL
: Copyright (C) 1999 Intel Corporation.
:
: This software and the related documents are Intel copyrighted materials,
: and your use of them is governed by the express license under which they
: were provided to you ("License"). Unless the License provides otherwise,
: you may not use, modify, copy, publish, distribute, disclose or transmit
: this software or the related documents without Intel's prior written
: permission.
:
: This software and the related documents are provided as is, with no
: express or implied warranties, other than those that are expressly stated
: in the License.
:
: @par Specification Reference:
: **/
> Please follow the correct copyright format for open source code. […]
Acknowledged
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Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#37).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL
using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/37
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Hello Felix Held, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83419?usp=email
to look at the new patch set (#38).
Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
mb/google/fatcat: Add Panther Lake SOC support
Details:
- This patch updates the original google/fatcat support added
with Meteor Lake support as a workaround.
- Adds initial support to build google/fatcat for Panther Lake SOC based
board till bootblock stage.
BUG=b:348678529
TEST=Able to build the google/fatcat and boot to bootblock stage
using Intel® Simics® Pre Silicon Simulation platform for PTL.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/mainboard.c
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
4 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/38
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