coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/cml, pci_ids: Fix IDs for UHD 610/630 S/H
by Maxim (Code Review) 04 Aug '24

04 Aug '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83708?usp=email to look at the new patch set (#5). Change subject: soc/intel/cml, pci_ids: Fix IDs for UHD 610/630 S/H ...................................................................... soc/intel/cml, pci_ids: Fix IDs for UHD 610/630 S/H https://web.archive.org/web/20240731150632/https://devicehunt.com/view/ type/pci/vendor/8086/device/9BA8 8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] 8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610] [*] https://web.archive.org/web/20230928015210/https://devicehunt.com/view/ type/pci/vendor/8086/device/9BA4 8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] 8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610] [*] https://web.archive.org/web/20230924050019/https://devicehunt.com/view/ type/pci/vendor/8086/device/9BC8 https://web.archive.org/web/20240520163236/https://devicehunt.com/view/ type/pci/vendor/8086/device/9BC5 8086:9BC5 - Comet Lake-S GT2 [UHD Graphics 630] 8086:9BC8 - Comet Lake-S GT2 [UHD Graphics 630] [*] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html Some IDs are missing in the documentation [*], others were initially incorrect, for example: https://web.archive.org/web/20231004011832/https://devicehunt.com/view/ type/pci/vendor/8086/device/9B44 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers This device is clearly not graphical. Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 8 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83708/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83708?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Gerrit-Change-Number: 83708 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cml, pci_ids: Fix IDs for UHD 610/630 S/H
by Maxim (Code Review) 04 Aug '24

04 Aug '24

Maxim has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83708?usp=email ) Change subject: soc/intel/cml, pci_ids: Fix IDs for UHD 610/630 S/H ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83708?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Gerrit-Change-Number: 83708 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Aug 2024 07:10:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 only
by Subrata Banik (Code Review) 04 Aug '24

04 Aug '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83707?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 only ...................................................................... mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 only This patch introduces the following changes, - Remove TCSS XHCI (USB 3.x) devicetree settings - Update Over Current (OC) & USB 2.0 config - Update TCSS-XHCI capabilities BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 12 insertions(+), 16 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 6173bc7..35cf84b 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -5,6 +5,7 @@ register "sagv" = "SaGv_Enabled" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port C0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 @@ -30,6 +31,11 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable Type-A port register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -251,27 +257,17 @@ end end device ref pmc hidden end - device ref tcss_xhci on - chip drivers/usb/acpi - device ref tcss_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" - device ref tcss_usb3_port1 on end - end - end - end - end + device ref tcss_xhci off end + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-C Charging Port C0 (MLB)"" + register "type" = "UPC_TYPE_PROPRIETARY" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(0, 2))" device ref usb2_port1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 10 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove PMC MUX setting
by Subrata Banik (Code Review) 04 Aug '24

04 Aug '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83760?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/nova: Remove PMC MUX setting ...................................................................... mb/google/brya/var/nova: Remove PMC MUX setting This patch removes the PMC MUX related setting from devicetree as Nova doesn't include a MUX for it's USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Signed-off-by: Pranava Y N <pranavayn(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 1 insertion(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 950bb9b..6173bc7 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -247,21 +247,10 @@ device ref gspi1 off end device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] device pnp 0c09.0 on end end end - device ref pmc hidden - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end - end - end - end - end + device ref pmc hidden end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/83760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Gerrit-Change-Number: 83760 Gerrit-PatchSet: 3 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: [only for test] use C23 dialect
by Elyes Haouas (Code Review) 04 Aug '24

04 Aug '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83502?usp=email ) Change subject: [only for test] use C23 dialect ...................................................................... Abandoned duplicated -- To view, visit https://review.coreboot.org/c/coreboot/+/83502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f1330cbac46ba580c541319dea1de154d47846 Gerrit-Change-Number: 83502 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Subrata Banik (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Felix Held, Paul Menzel, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 42: (1 comment) Patchset: PS37: > Yesterday, I attempted to ensure that the fatcat mainboard could be built using only the minimal code for the PTL SOC. However, it appears that due to the introduction of common code and the separation of the various stage dependencies, we will not be able to build the fatcat mainboard code using only the bootblock/minimal code. In order to build fatcat correctly, we must land the code in the following order: > > 1. bootblock > 2. romstage > 3. gpio > 4. ramstage > 5. ACPI/ASL > 6. Finally, google/fatcat > > Therefore, my recommendation is to follow this order and keep the mb code at the top of each CL. This way, we can only land the CLs from the bottom of #6, which will ensure that the fatcat mainboard build is successful. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 42 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 03 Aug 2024 17:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Subrata Banik (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Felix Held, Paul Menzel, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 42: (1 comment) Patchset: PS31: > I am working on it. I just hope you should follow directions from https://review.coreboot.org/c/coreboot/+/83419/comments/801533d3_b71e7576 to prepare buildable recipe. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 42 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 03 Aug 2024 17:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
by Subrata Banik (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email ) Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile ...................................................................... Patch Set 8: (1 comment) Patchset: PS5: > Hi Subrata,can we land this CL to +2? and merge it. Please follow the recommendation https://review.coreboot.org/c/coreboot/+/83419/comments/36439948_53d74701 -- To view, visit https://review.coreboot.org/c/coreboot/+/83732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Gerrit-Change-Number: 83732 Gerrit-PatchSet: 8 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Sat, 03 Aug 2024 17:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Subrata Banik (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Felix Held, Paul Menzel, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... Patch Set 42: (1 comment) Patchset: PS42: As I have said, this CL should always be at the top of the other SoC CLs, and I will only be able to merge CLs from the bottom of the patch train when I see that this CL has been promoted to V+1. I hope this is clear for you to prepare the recipe? At present I don't see that is happening. -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 42 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 03 Aug 2024 17:34:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
by Krishna P Bhat D (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Saurabh Mishra, Subrata Banik. Krishna P Bhat D has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email ) Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83732/comment/0b034369_78d962ed?us… : PS8, Line 10: - Skeleton files to complie google/fatcat mainboard. nit: compile File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h: https://review.coreboot.org/c/coreboot/+/83732/comment/06a08b27_61c1de3a?us… : PS8, Line 69: Remove the additional blank line at the end of all header files. -- To view, visit https://review.coreboot.org/c/coreboot/+/83732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Gerrit-Change-Number: 83732 Gerrit-PatchSet: 8 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sat, 03 Aug 2024 17:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit August 2024