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Change subject: mb/google/brox: Boot to kernel without battery
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83752/comment/4534117a_a01cecee?us… :
PS3, Line 7: Boot to kernel without battery
Maybe:
> Fix booting to kernel without battery
https://review.coreboot.org/c/coreboot/+/83752/comment/72849276_86c62512?us… :
PS3, Line 8:
Please start by describing the problem. Does it hang in Linux?
https://review.coreboot.org/c/coreboot/+/83752/comment/e1edbebb_83f4ec09?us… :
PS3, Line 9: Set Boot frequency UPD to 1 to avoid higher PL2 power draw when
: only adaptor is connected with battery removed or disconnected.
: Reduce PL4 value to overcome power spikes from SoC during boot.
: Remove Psys implementation since it impacts active state platform
: performance.
If you enumerate things, please format this as a list.
https://review.coreboot.org/c/coreboot/+/83752/comment/a82c7206_f1564795?us… :
PS3, Line 18: 65W,45W
Please add a space after the comma.
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,274 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/44
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,274 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/43
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Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83732/comment/1583d94d_f55d066e?us… :
PS8, Line 10: - Skeleton files to complie google/fatcat mainboard.
> nit: compile
Acknowledged
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/6a8eb4fa_adad2b66?us… :
PS8, Line 69:
> Remove the additional blank line at the end of all header files.
Acknowledged
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Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 42:
(1 comment)
Patchset:
PS37:
> > Yesterday, I attempted to ensure that the fatcat mainboard could be built using only the minimal c […]
Sure Subrata.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/42
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