coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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3913 discussions

[M] Change in coreboot[main]: util/autoport: Put devicetree devices above chips
by Angel Pons (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Nicholas Chin, Nico Huber. Angel Pons has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/82406?usp=email ) Change subject: util/autoport: Put devicetree devices above chips ...................................................................... Patch Set 5: (1 comment) File util/autoport/main.go: https://review.coreboot.org/c/coreboot/+/82406/comment/231509f0_e0de05e1?us… : PS3, Line 307: MatchDev(&dev.Children[idx]) > It seems to work. […] Yep, works as expected. Thanks for testing! -- To view, visit https://review.coreboot.org/c/coreboot/+/82406?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dc2ff13182ff9d92141b1736796749cea49d23a Gerrit-Change-Number: 82406 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Aug 2024 17:36:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: util/autoport: Put devicetree devices above chips
by Nicholas Chin (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Angel Pons, Nico Huber. Nicholas Chin has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/82406?usp=email ) Change subject: util/autoport: Put devicetree devices above chips ...................................................................... Patch Set 5: (1 comment) File util/autoport/main.go: https://review.coreboot.org/c/coreboot/+/82406/comment/10130982_b8c418b7?us… : PS3, Line 307: MatchDev(&dev.Children[idx]) > Updated but haven't had the chance to test. It seems to work. Tested it on logs from the Latitude E6430 (Ivy Bridge) and EliteDesk 800 G1 (Haswell) ``` device domain 0x0 on device ref host_bridge on # Host bridge Host bridge subsystemid 0x1028 0x0534 end device ref peg10 off # PEG end device ref igd on # iGPU subsystemid 0x1028 0x0534 end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ``` ``` device domain 0x0 on ops haswell_pci_domain_ops device pci 00.0 on # Desktop Host bridge subsystemid 0x103c 0x8027 end device pci 01.0 off # PCIe Bridge for discrete graphics end device pci 02.0 off # Internal graphics end device pci 03.0 off # Mini-HD audio end chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82406?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dc2ff13182ff9d92141b1736796749cea49d23a Gerrit-Change-Number: 82406 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Aug 2024 17:33:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
by Nigel Tao (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Felix Singer, Jonathon Hall, Martin L Roth, Nico Huber, Paul Menzel. Nigel Tao has posted comments on this change by Jonathon Hall. ( https://review.coreboot.org/c/coreboot/+/83476?usp=email ) Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: > I guess I was thinking about the resolution (file(1) should be able to print it?). […] The Wuffs calculation goes like this: Usually (but not always), JPEG uses 4:2:0 chroma subsampling (https://en.wikipedia.org/wiki/Chroma_subsampling). For a 1024x768 JPEG, this means that there are: - 1024x768 Y (luma) samples - 512x384 Cb (chroma-blue) samples - 512x384 Cr (chroma-red) samples Each sample is one byte, hence ((1024x768) + (512x384) + (512x384)) = 1179648 bytes of "work buffer" memory is needed. That's with Wuffs `0.4.0-alpha.2`. As I said in the other comment, if you upgrade to `0.4.0-alpha.6` then the required work buffer size can drop to zero and, IIUC, you won't need this Kconfig change, since `src/lib/jpeg.c` won't need to malloc or free any more. PS2: > But if overestimating memory requirements (by a few MB) is problematic for coreboot, I can do some thinking about a leaner (but more complicated) API. OK, I have a leaner (and not actually much more complicated) API. Coreboot's copy of Wuffs (`src/vendorcode/wuffs/wuffs-v0.4.c`) is currently at `0.4.0-alpha.2`. If you upgrade (copy `release/c/wuffs-v0.4.c` from https://github.com/google/wuffs) to the freshly git-pushed `0.4.0-alpha.6` then you can now opt in to a lower-quality JPEG decoding (specifically: box filtering instead of triangle filtering when chroma upsampling) which should drop the minimum Wuffs work area requirement (its "work buffer" length) for sequential (not progressive) JPEGs to zero: no heap allocation necessary anymore. I assume Coreboot can simply decide to not support progressive JPEGs in bootsplash. If you upgrade, try this `src/lib/jpeg.c` patch (but I don't know how to test it myself): ``` diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 242cf0ca..2fe7ffdb 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Provide a simple API around the Wuffs JPEG decoder - * Uses the heap (and lots of it) for the image-size specific - * work buffer, so ramstage-only. + * Provide a simple API around the Wuffs JPEG decoder. */ #include <stdint.h> @@ -84,6 +82,11 @@ int jpeg_decode(unsigned char *filedata, size_t filesize, unsigned char *pic, if (status.repr) { return JPEG_DECODE_FAILED; } + status = wuffs_jpeg__decoder__set_quirk(&dec, WUFFS_BASE__QUIRK_QUALITY, + WUFFS_BASE__QUIRK_QUALITY__VALUE__LOWER_QUALITY); + if (status.repr) { + return JPEG_DECODE_FAILED; + } wuffs_base__image_config imgcfg; wuffs_base__io_buffer src = wuffs_base__ptr_u8__reader(filedata, filesize, true); @@ -104,19 +107,16 @@ int jpeg_decode(unsigned char *filedata, size_t filesize, unsigned char *pic, return JPEG_DECODE_FAILED; } - uint64_t workbuf_len_min_incl = wuffs_jpeg__decoder__workbuf_len(&dec).min_incl; - uint8_t *workbuf_array = malloc(workbuf_len_min_incl); - if ((workbuf_array == NULL) && workbuf_len_min_incl) { + if (wuffs_jpeg__decoder__workbuf_len(&dec).min_incl > 0) { + // Setting WUFFS_BASE__QUIRK_QUALITY__VALUE__LOWER_QUALITY means that + // we can get a zero workbuf_len for common (sequential) JPEGs. No + // additional memory required. We choose not to support rarer + // (progressive) JPEGs. return JPEG_DECODE_FAILED; } - wuffs_base__slice_u8 workbuf = - wuffs_base__make_slice_u8(workbuf_array, workbuf_len_min_incl); status = wuffs_jpeg__decoder__decode_frame(&dec, &pixbuf, &src, - WUFFS_BASE__PIXEL_BLEND__SRC, workbuf, NULL); - - free(workbuf_array); - + WUFFS_BASE__PIXEL_BLEND__SRC, wuffs_base__empty_slice_u8(), NULL); if (status.repr) { return JPEG_DECODE_FAILED; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4348d39effbc16c1b42ab01bcf1e4ec5d652fa9 Gerrit-Change-Number: 83476 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nigel Tao <nigeltao(a)golang.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Sun, 04 Aug 2024 14:54:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Comment-In-Reply-To: Nigel Tao <nigeltao(a)golang.org>

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[L] Change in coreboot[main]: mb/dell/optiplex_9020: Implement late HWM initialization
by Angel Pons (Code Review) 04 Aug '24

04 Aug '24

Angel Pons has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email ) Change subject: mb/dell/optiplex_9020: Implement late HWM initialization ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81529/comment/af54459d_de435606?us… : PS11, Line 9: There are 4 different chassis types specified by vendor firmware, each : with a slightly different HWM configuration. > I believe the GPIO to chassis type mapping is in "DellChassisConfigDxe". […] It's (U)EFI, overengineering is the norm... -- To view, visit https://review.coreboot.org/c/coreboot/+/81529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Gerrit-Change-Number: 81529 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Aug 2024 09:25:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Máté Kukri <km(a)mkukri.xyz> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/dell/optiplex_9020: Implement late HWM initialization
by Máté Kukri (Code Review) 04 Aug '24

04 Aug '24

Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email ) Change subject: mb/dell/optiplex_9020: Implement late HWM initialization ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81529/comment/6a23a197_424f156d?us… : PS11, Line 9: There are 4 different chassis types specified by vendor firmware, each : with a slightly different HWM configuration. > Out of curiosity, where are those specified in the vendor firmware? I believe the GPIO to chassis type mapping is in "DellChassisConfigDxe". But to understand the entire HWM configuration and GPIO logic, there are many modules used: - DxeGpioControl (GPIO abstraction) - DxeGpioPolicy (GPIO pin definitions) - DxeSbGpioControl (PCH GPIO driver) - DxeSioGpioControl (SIO GPIO driver, not implemented in coreboot) - DellChassisConfigDxe (GPIO -> chassis mapping) - DxeSioEmi (for talking to the SIO) - DxeHwmDriver (the actual HWM configuration logic) - And probably a few more I forgot about..... I don't think I even have to mention the fact that this is "slightly" over-engineered in the vendor firmware, the length of the above list should make it obvious. -- To view, visit https://review.coreboot.org/c/coreboot/+/81529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Gerrit-Change-Number: 81529 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Aug 2024 09:23:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 45: (1 comment) File src/soc/intel/pantherlake/bootblock/pcd.c: https://review.coreboot.org/c/coreboot/+/83354/comment/924c12f6_9457cce7?us… : PS36, Line 129: if (pmc_reg_value != 0xffffffff) { > Sure, i have added one check implementation, printing the resultant value and returning. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 45 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 04 Aug 2024 08:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83354?usp=email to look at the new patch set (#45). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Includes additional minimal code required to compile the PTL SoC and google/fatcat mainbaord. 5. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/bootblock/bootblock.c A src/soc/intel/pantherlake/bootblock/pcd.c A src/soc/intel/pantherlake/bootblock/report_platform.c A src/soc/intel/pantherlake/espi.c A src/soc/intel/pantherlake/include/soc/bootblock.h A src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pci_devs.h A src/soc/intel/pantherlake/include/soc/pcr_ids.h A src/soc/intel/pantherlake/include/soc/pm.h A src/soc/intel/pantherlake/include/soc/smbus.h A src/soc/intel/pantherlake/include/soc/soc_info.h A src/soc/intel/pantherlake/soc_info.c 15 files changed, 1,273 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 45 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range
by Paul Menzel (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO high range ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83538/comment/1be9af2b_ba3d3f0e?us… : PS4, Line 13: belonged belong*ing*? https://review.coreboot.org/c/coreboot/+/83538/comment/c397c079_461ca9c4?us… : PS4, Line 16: Paste an example of cluttered coverage? https://review.coreboot.org/c/coreboot/+/83538/comment/6a07ca0f_cd5c12a5?us… : PS4, Line 31: tsc: Detected 2000.000 MHz processor : last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 : x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT : WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. : ------------[ cut here ]------------ : WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 : ... : Call Trace: : ? 0xffffffff8f600000 : ? setup_arch+0x4bb/0xaed : ? printk+0x53/0x6a : ? start_kernel+0x55/0x507 : ? load_ucode_intel_bsp+0x1c/0x4d : ? secondary_startup_64_no_verify+0xc2/0xcb : random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 : ---[ end trace 0e56686fd458f0c5 ]--- : update e820 for mtrr : modified physical RAM map: : modified: [mem 0x0000000000000000-0x0000000000000fff] reserved : ... : modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved : last_pfn = 0x6354e max_arch_pfn = 0x10000000000 : Memory KASLR using RDRAND RDTSC... : x2apic: enabled by BIOS, switching to x2apic ops : Using GB pages for direct mapping : ... : Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] : DMA zone: 28769 pages in unavailable ranges : DMA32 zone: 19122 pages in unavailable ranges : BUG: unable to handle page fault for address: ff24b56eba60cff8 : BAD : Oops: 0000 [#1] SMP NOPTI : CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 : ... : Call Trace: : ? set_pte_vaddr_p4d+0x24/0x35 : ? __native_set_fixmap+0x21/0x28 : ? map_vsyscall+0x35/0x56 : ? setup_arch+0xa00/0xaed : ? printk+0x53/0x6a : ? start_kernel+0x55/0x507 : ? load_ucode_intel_bsp+0x1c/0x4d : ? secondary_startup_64_no_verify+0xc2/0xcb : CR2: ff24b56eba60cff8 : ---[ end trace 0e56686fd458f0c6 ]--- : RIP: 0010:fill_pud+0xa/0x62 : ... : Kernel panic - not syncing: Attempted to kill the idle task! : ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Linux 5.10.50 seems pretty old. Does it happen with current Linux 6.10 kernel too? -- To view, visit https://review.coreboot.org/c/coreboot/+/83538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Gerrit-Change-Number: 83538 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 04 Aug 2024 07:58:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/dell/optiplex_9020: Implement late HWM initialization
by Paul Menzel (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Mate Kukri. Paul Menzel has posted comments on this change by Mate Kukri. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email ) Change subject: mb/dell/optiplex_9020: Implement late HWM initialization ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81529/comment/eccb7812_989bd261?us… : PS11, Line 9: There are 4 different chassis types specified by vendor firmware, each : with a slightly different HWM configuration. Out of curiosity, where are those specified in the vendor firmware? -- To view, visit https://review.coreboot.org/c/coreboot/+/81529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Gerrit-Change-Number: 81529 Gerrit-PatchSet: 11 Gerrit-Owner: Mate Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Mate Kukri <km(a)mkukri.xyz> Gerrit-Comment-Date: Sun, 04 Aug 2024 07:54:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/inte/cnvi: Add AOLX Method
by Paul Menzel (Code Review) 04 Aug '24

04 Aug '24

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83716?usp=email ) Change subject: soc/inte/cnvi: Add AOLX Method ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83716/comment/68d56021_3ea47cf0?us… : PS5, Line 12: Tested how? -- To view, visit https://review.coreboot.org/c/coreboot/+/83716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeafb2b6e8a702430dcf10eb28bfeb9f77aa29b4 Gerrit-Change-Number: 83716 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 04 Aug 2024 07:52:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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