Attention is currently required from: Elyes Haouas, Martin L Roth.
Hello Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81419?usp=email
to look at the new patch set (#17).
Change subject: [for test] test upgrade crossgcc
......................................................................
[for test] test upgrade crossgcc
Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/acpica-unix2-20240321_iasl.patch
R util/crossgcc/patches/gcc-15-20240728_asan_shadow_offset_callback.patch
R util/crossgcc/patches/gcc-15-20240728_gnat.patch
R util/crossgcc/patches/gcc-15-20240728_libcpp.patch
R util/crossgcc/patches/gcc-15-20240728_libgcc.patch
R util/crossgcc/patches/gcc-15-20240728_musl_poisoned_calloc.patch
R util/crossgcc/patches/gcc-15-20240728_rv32iafc.patch
D util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
A util/crossgcc/sum/acpica-unix2-20240321.tar.gz.cksum
D util/crossgcc/sum/clang-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/cmake-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/cmake-3.29.3.tar.gz.cksum
A util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum
D util/crossgcc/sum/compiler-rt-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/gcc-14.1.0.tar.xz.cksum
A util/crossgcc/sum/gcc-15-20240728.tar.xz.cksum
D util/crossgcc/sum/libunwind-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/lld-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum
D util/crossgcc/sum/llvm-18.1.6.src.tar.xz.cksum
A util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum
28 files changed, 30 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/17
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Gerrit-Change-Number: 81419
Gerrit-PatchSet: 17
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Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83760?usp=email )
Change subject: mb/google/brya/var/nova: Remove PMC MUX setting
......................................................................
mb/google/brya/var/nova: Remove PMC MUX setting
This patch removes the PMC MUX related setting from devicetree as Nova
doesn't include a MUX for it's USB-C port.
BUG=b:348332200
TEST=Able to build google/nova
Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
---
M src/mainboard/google/brya/variants/nova/overridetree.cb
1 file changed, 1 insertion(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83760/1
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index 950bb9b..6173bc7 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -247,21 +247,10 @@
device ref gspi1 off end
device ref pch_espi on
chip ec/google/chromeec
- use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
- device ref pmc hidden
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port1 as usb2_port
- use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
- end
- end
- end
- end
+ device ref pmc hidden end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
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Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email )
Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 37:
(1 comment)
Patchset:
PS37:
Yesterday, I attempted to ensure that the fatcat mainboard could be built using only the minimal code for the PTL SOC. However, it appears that due to the introduction of common code and the separation of the various stage dependencies, we will not be able to build the fatcat mainboard code using only the bootblock/minimal code. In order to build fatcat correctly, we must land the code in the following order:
1. bootblock
2. romstage
3. gpio
4. ramstage
5. ACPI/ASL
6. Finally, google/fatcat
Therefore, my recommendation is to follow this order and keep the mb code at the top of each CL. This way, we can only land the CLs from the bottom of #6, which will ensure that the fatcat mainboard build is successful.
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Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81567?usp=email )
Change subject: soc/intel/xeon_sp: Add PCIe root port driver
......................................................................
Patch Set 11: Code-Review+2
(4 comments)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/81567/comment/48ab382d_c15a57a0?us… :
PS11, Line 121: is_pci_bridge
This should only be necessary for device that do not have it's own `acpi_name` function ptr in `struct device_operations`. See comment on pcie_root_port.c
File src/soc/intel/xeon_sp/pcie_root_port.c:
https://review.coreboot.org/c/coreboot/+/81567/comment/c3d8a0d0_763f7f76?us… :
PS11, Line 10: pcie_device_set_acpi_name
Rename to `pcie_device_get_acpi_name` and handle downstream devices here. `acpi_device_name()` will call this function for each downstream device to get their name.
https://review.coreboot.org/c/coreboot/+/81567/comment/df37f784_0edd6291?us… :
PS11, Line 48: }
Missing call to pci_dev_init().
https://review.coreboot.org/c/coreboot/+/81567/comment/3a788528_a9ec43e7?us… :
PS11, Line 71: acpi_fill_ssdt
add `.acpi_name = pcie_device_get_acpi_name,`
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Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83652?usp=email )
Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
arch/arm64/armv8/mmu: Improve log format
Currently we use "%p" to print the address, which results in different
string lengths, depending on the value of the address. To improve
readability of the printed addresses in the log, change the format to
"0x%013lx", so that the length of the printed addresses will be
consistent.
In addition, print the level of the translation table when setting up a
new table.
Example log:
Backing address range [0x0000000000000:0x1000000000000) with new L0 ...
Mapping address range [0x0000000000000:0x0000200000000) as ...
Backing address range [0x0000000000000:0x0008000000000) with new L1 ...
Mapping address range [0x0000000100000:0x0000000130000) as ...
Backing address range [0x0000000000000:0x0000040000000) with new L2
Backing address range [0x0000000000000:0x0000000200000) with new L3
Mapping address range [0x0000000107000:0x0000000108000) as ...
Mapping address range [0x0000000200000:0x0000000300000) as ...
Backing address range [0x0000000000000:0x0000000200000) with new L3 ...
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83652
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/arch/arm64/armv8/mmu.c
1 file changed, 30 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 0f84146..65d0f92 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -11,6 +11,9 @@
#include <arch/mmu.h>
#include <console/console.h>
+/* 12 hex digits (48 bits VA) plus 1 for exclusive upper bound. */
+#define ADDR_FMT "0x%013lx"
+
/* This just caches the next free table slot (okay to do since they fill up from
* bottom to top and can never be freed up again). It will reset to its initial
* value on stage transition, so we still need to check it for UNUSED_DESC. */
@@ -54,6 +57,25 @@
return attr;
}
+/* Func : table_level_name
+ * Desc : Get the descriptions table level name from the given size.
+ */
+static const char *table_level_name(size_t xlat_size)
+{
+ switch (xlat_size) {
+ case L0_XLAT_SIZE:
+ return "L0";
+ case L1_XLAT_SIZE:
+ return "L1";
+ case L2_XLAT_SIZE:
+ return "L2";
+ case L3_XLAT_SIZE:
+ return "L3";
+ default:
+ return "";
+ }
+}
+
/* Func : setup_new_table
* Desc : Get next free table from TTB and set it up to match old parent entry.
*/
@@ -66,9 +88,12 @@
}
void *frame_base = (void *)(desc & XLAT_ADDR_MASK);
- printk(BIOS_DEBUG, "Backing address range [%p:%p) with new page"
- " table @%p\n", frame_base, frame_base +
- (xlat_size << BITS_RESOLVED_PER_LVL), next_free_table);
+ const char *level_name = table_level_name(xlat_size);
+ printk(BIOS_DEBUG,
+ "Backing address range [" ADDR_FMT ":" ADDR_FMT ") with new %s table @%p\n",
+ (uintptr_t)frame_base,
+ (uintptr_t)frame_base + (xlat_size << BITS_RESOLVED_PER_LVL),
+ level_name, next_free_table);
if (!desc) {
memset(next_free_table, 0, GRANULE_SIZE);
@@ -213,8 +238,8 @@
uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
- start, start + size);
+ printk(BIOS_INFO, "Mapping address range [" ADDR_FMT ":" ADDR_FMT ") as ",
+ (uintptr_t)start, (uintptr_t)start + size);
print_tag(BIOS_INFO, tag);
sanity_check(base_addr, temp_size);
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Change subject: arch/arm64/armv8/mmu: Improve log format
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83652/comment/dee9e8bf_4c037079?us… :
PS2, Line 9: When using format string with "%p", "(nil)" will be printed for address
> I mean, in that case I feel like %013p would fit better than casting everything. […]
"%013p" doesn't work:
```
src/arch/arm64/armv8/mmu.c:93:9: error: '0' flag used with '%p' gnu_printf format [-Werror=format=]
```
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