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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
Patch Set 24:
(1 comment)
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/83705/comment/d1136750_e0f729e3?us… :
PS20, Line 105: config CHROMEOS_ENABLE_ESOL
> > So are you saying that the Kconfig only exists so that you can extract the `config` file from CBFS […]
Updated
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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
Patch Set 3: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83737?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE_V2
......................................................................
payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE_V2
Official EDK2 repository has VARIABLE_SUPPORT defaulting to EMU in
UefiPayloadPkg, switch it to SMMSTORE if coreboot is built with
SMMSTOREv2.
This removes custom default of EDK2_CUSTOM_BUILD_PARAMS for
EDK2_REPO_MRCHROMEBOX which is unnecessary now.
Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83737
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M payloads/external/edk2/Kconfig
M payloads/external/edk2/Makefile
2 files changed, 3 insertions(+), 1 deletion(-)
Approvals:
Maximilian Brune: Looks good to me, approved
Matt DeVillier: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 57e38b9..0f88d36 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -319,7 +319,7 @@
config EDK2_CUSTOM_BUILD_PARAMS
string "edk2 additional custom build parameters"
- default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
+ default ""
help
edk2 has build options that are not modified by coreboot, and these can be
found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 3966b91..e198623 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -69,8 +69,10 @@
ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
endif
+# VARIABLE_SUPPORT = EMU
# MAX_VARIABLE_SIZE = 0x10000
ifeq ($(CONFIG_SMMSTORE_V2),y)
+BUILD_STR += -D VARIABLE_SUPPORT=SMMSTORE
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize=0x8000
endif
# PCIE_BASE_ADDRESS = 0
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Change subject: drivers/intel/fsp2: Add config for FSP uGOP eSOL
......................................................................
drivers/intel/fsp2: Add config for FSP uGOP eSOL
This patch introduces a new configuration option,
FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP
support using FSP-M for the early sign-of-life feature in SOC.
BUG=NA
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83770/9
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign-of-life config option when
libgfx or uGOP is enabled for early graphics initialization.
BUG=b:352651132
TEST=Able to build google/rex and google/tivviks
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/alderlake/romstage/ux.c
M src/vendorcode/google/chromeos/Kconfig
2 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/24
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Change subject: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
......................................................................
soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
This patch replaces the platform-specific Meteor Lake early
sign-of-life configuration with a generic FSP uGOP eSOL configuration.
BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
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---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83769/19
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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83815/comment/4e2d9fe0_dadb7999?us… :
PS2, Line 100: PSP_NVRAM_BASE
> oh, this should have been PSP_RPMC_NVRAM_BASE
Done
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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
and Stoneyridge which doesn't use/support this.
If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file,
the start and length of it in the flash will be passed to amdfwtool
which then adds the base and length to the corresponding type 0x54 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f
---
M src/soc/amd/cezanne/Makefile.mk
M src/soc/amd/glinda/Makefile.mk
M src/soc/amd/mendocino/Makefile.mk
M src/soc/amd/phoenix/Makefile.mk
M src/soc/amd/picasso/Makefile.mk
5 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83815/3
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Change subject: soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83815/comment/60d8f31e_96fbc7e0?us… :
PS2, Line 100: PSP_NVRAM_BASE
oh, this should have been PSP_RPMC_NVRAM_BASE
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Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Comment-Date: Thu, 08 Aug 2024 17:43:10 +0000
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