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Change subject: intel/alderlake: Drop redundant Client/AlderLake* FSP paths
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83826/comment/adb2538d_909b6e5b?us… :
PS1, Line 413: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
> > Either way we would need additional infrastructure to track which boards
> > shouldn't get the update. And after all, this is the *main* branch. So we
> > should really ask, is it worth the hassle?
>
> I'm leaving this upto you if you think it's okay to enforce all ADL device to switch to converged FW (with RPL).
>
> I have shared my side of the story where forcing ADL to RPL migration involves validation cost and it should leave upto the platform owners if they are okay to offer RPL FSP for their older ADL device or not.
I don't see us enforcing anything. There is no policy that I know of that says
platform owners have to validate the upstream main branch. And if anybody wants
to go through and add additional infrastructure to track more FSP versions, I
wouldn't stop them (in fact, I've argued in the past that one submodule pointer
per platform or even per board might be better).
Subrata, please help me understand the problem you see better to avoid future
friction:
* Do you / does Google validate the upstream main branch with configs that include `CONFIG_FSP_USE_REPO=y`?
* Do you know about anybody else who does?
* Does your validation differ for minor FSP updates (that we can have with any submodule pointer update) vs. switching from ADL to converged RPL?
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Rishika Raj, Weimin Wu.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Weimin Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Weimin Wu, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/teliks: Add DP AUX BIAS connect
......................................................................
mb/google/nissa/var/teliks: Add DP AUX BIAS connect
Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.
BUG=b:352263941
TEST=DP function of MB and DB workable
Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/teliks/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83829/2
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Change subject: soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
......................................................................
soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/cse/Makefile.mk
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83831/2
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Subrata Banik has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/83826?usp=email )
Change subject: intel/alderlake: Drop redundant Client/AlderLake* FSP paths
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83826/comment/d480225a_0d8c4091?us… :
PS1, Line 413: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
> Either way we would need additional infrastructure to track which boards
> shouldn't get the update. And after all, this is the *main* branch. So we
> should really ask, is it worth the hassle?
I'm leaving this upto you if you think it's okay to enforce all ADL device to switch to converged FW (with RPL).
I have shared my side of the story where forcing ADL to RPL migration involves validation cost and it should leave upto the platform owners if they are okay to offer RPL FSP for their older ADL device or not.
marking it resolved
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Change subject: soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
......................................................................
Patch Set 1: Code-Review+2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83831?usp=email )
Change subject: soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
......................................................................
soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overridding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overridding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/cse/Makefile.mk
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83831/1
diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk
index d41d735..9196cf8 100644
--- a/src/soc/intel/common/block/cse/Makefile.mk
+++ b/src/soc/intel/common/block/cse/Makefile.mk
@@ -91,6 +91,7 @@
$(CSE_LITE_ME_RW)-compression := LZMA
endif
+ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"")
INPUT_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
TEMP_FILE := $(shell mktemp)
OFFSETS := 16 18 20 22 # Offsets for CSE version components
@@ -105,6 +106,10 @@
rm -f $(TEMP_FILE)
$(eval CSE_RW_CBFS_VERSION := $(shell printf "%d.%d.%d.%d" $(CSE_VERSION_MAJOR)$(CSE_VERSION_MINOR)$(CSE_VERSION_HOTFIX)$(CSE_VERSION_BUILD)))
@echo '$(CSE_RW_CBFS_VERSION)' > $@
+else
+$(obj)/cse_rw.version:
+ @echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@
+endif
CSE_RW_VERSION = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME))
regions-for-file-$(CSE_RW_VERSION) = FW_MAIN_A,FW_MAIN_B
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Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Subrata Banik.
Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/83826?usp=email )
Change subject: intel/alderlake: Drop redundant Client/AlderLake* FSP paths
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83826/comment/b16df8f1_6fcb2aa3?us… :
PS1, Line 413: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
> > No. Again, `3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/` points to Raptor […]
Either way we would need additional infrastructure to track which boards
shouldn't get the update. And after all, this is the *main* branch. So we
should really ask, is it worth the hassle?
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Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, Sumeet R Pawnikar.
Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A),
hence, provide a config for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
to observe whether the value is changing as expected.
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/16
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